Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance

Jeff Mueller, R. Saleh
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引用次数: 4

Abstract

Synchronous clock distribution continues to be the dominant timing methodology for VLSI designs. As processes shrink, clock speeds increase, and die sizes grow, more-and-more of the clock period is lost to skew and jitter budgets. We propose to improve clock performance by focusing on the single, critical clock edge while relaxing requirements of the non-critical edge. A novel re-design of the traditional clock buffer is proposed as a drop-in replacement for existing clock distribution networks, yielding timing performance improvements of over 20% in latency and skew and up to 30% in jitter; alternatively, these timing advantages could be traded off to reduce clock buffer area and power by 33% and 12%, respectively.
单边时钟(SEC)分布改善延迟,倾斜和抖动性能
同步时钟分配仍然是VLSI设计的主要时序方法。随着工艺的缩减、时钟速度的提高和晶片尺寸的增大,越来越多的时钟周期损失在倾斜和抖动预算上。我们建议通过关注单个关键时钟边缘来提高时钟性能,同时放宽对非关键边缘的要求。提出了对传统时钟缓冲器的一种新颖的重新设计,作为现有时钟分配网络的替代方案,其时序性能在延迟和倾斜方面提高了20%以上,在抖动方面提高了30%;或者,可以交换这些时序优势,以分别减少33%和12%的时钟缓冲区和功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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