亚100纳米PDSOI和双栅技术的最佳双vt设计

A. Bansal, Jae-Joon Kim, Keunwoo Kim, S. Mukhopadhyay, C. Chuang, K. Roy
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引用次数: 2

摘要

双vt CMOS是降低高性能VLSI电路漏功率的有效途径。在本文中,我们探索了双阈值电压晶体管设计在深度亚100纳米技术节点的技术设计空间。我们提出了一种实现高vt器件的技术-更长的栅极侧壁偏移间隔,以增加通道长度而不增加印刷栅极长度。在晶体管至基本逻辑栅极水平上,分析了所有双vt技术选项(增加通道掺杂、增加栅极长度和增加间隔层厚度)的有效性。结果表明,与长栅极长度和高掺杂器件相比,该技术具有更低的动态功耗和更低的性能损失。然而,我们提出的技术通过增加体掺杂来增加类似于高vt的额外制造掩膜。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies
Dual-VT CMOS is an effective way to reduce leakage power in high-performance VLSI circuits. In this paper, we explore the technology design space for dual-threshold voltage transistor design in deep sub-100 nm technology nodes. We propose a technique of achieving high-VT devices - longer gate sidewall offset spacers to increase the channel length without increasing the printed gate length. Effectiveness of all the dual-VT technology options - increasing channel doping, increasing gate length and proposed technique of increasing spacer thickness - are analyzed at transistor to basic logic gate level. Results indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body doping devices. Our proposed technique, however, incurs extra fabrication mask similar to high-VT by increasing body doping.
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