高能效、高性能算术单元电路

S. Agarwal, K. PavankumarV., R. Yokesh
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引用次数: 42

摘要

加法器和乘法器是通用微处理器中最重要的运算单元,也是功耗的主要来源。实现这些单元的架构风格多种多样,每种风格都有自己的优点和缺点。然而,由于持续的集成强度和便携式设备的需求不断增长,低功耗设计是首要的。此外,在功耗高的乘法器结构中,由于内部节点上的大量虚假转换,导致大量功率耗散。提出了一种基于互补通型晶体管逻辑(CPL)的全加法器结构,该结构比现有结构更快、更节能。我们还提出了一种利用分解逻辑实现乘法器电路的新技术,该技术通过减少内部节点上的杂散跃迁来提高速度并降低功耗。结合新的加法器结构和分解逻辑,乘法器结构的性能有了实质性的提高。借助这些最先进的设计,可以设计出高效的处理器,特别是数字信号处理器。我们使用TSPICE在台积电180纳米技术中进行了模拟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Energy-Efficient, High Performance Circuits for Arithmetic Units
Adders and multipliers are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Various architecture styles exist to implement these units, each having their own merits and demerits. However, due to continuing integrating intensity and growing needs of portable devices, low power design is of prime importance. In addition, much power is dissipated due to a large number of spurious transitions on internal nodes in power hungry multiplier structures. We present a new full adder structure based on complementary pass transistor logic (CPL) which is faster and more energy efficient than the existing structures. We also propose a new technique of implementing multiplier circuit using decomposition logic which improves speed and reduces power consumption by reducing the spurious transitions on internal nodes. Combined with the new adder structure and the decomposition logic, there is substantial improvement in the performance of the multiplier structures. With the help of these state of the art designs, it would be possible to design highly power efficient processors, especially digital signal processors. We have used TSPICE for simulation in the TSMC 180 nm technology.
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