An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products

Sabyasachi Das, S. Khatri
{"title":"An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products","authors":"Sabyasachi Das, S. Khatri","doi":"10.1109/VLSI.2008.18","DOIUrl":null,"url":null,"abstract":"In state-of-the-art digital signal processing (DSP) and graphics applications, the arithmetic sum-of-product (SOP) is an important and computationally intensive operation, consuming a significant amount of area, delay and power. This paper presents a new algorithmic approach to synthesize a non-timing critical SOP block in an area-efficient and power-efficient way, which can be very useful to reduce the size and power consumption of the non timing-critical portion in the design. We have divided the problem of generating the SOP into three parts: inversion-based creation of the BitClusters (sets of individual partial-product bits, which belong to the ith bitslice), propagation-based reduction of the BitClusters and selective-inversion based computation of the final sum result. Techniques used in these three steps help to reduce the implementation area and power consumption for the SOP block. Our experimental data shows that the SOP block generated by our approach is significantly smaller (8.59% on average) and marginally faster (0.42% on average) than the SOP block generated by a commercially available best-in-class datapath synthesis tool. In addition, our proposed SOP netlist consumes significantly less dynamic power (7.92% on average) and leakage power (5.65% on average) than the netlist generated by the synthesis tool. These improvements were verified on placed-and-routed designs as well.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st International Conference on VLSI Design (VLSID 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI.2008.18","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

In state-of-the-art digital signal processing (DSP) and graphics applications, the arithmetic sum-of-product (SOP) is an important and computationally intensive operation, consuming a significant amount of area, delay and power. This paper presents a new algorithmic approach to synthesize a non-timing critical SOP block in an area-efficient and power-efficient way, which can be very useful to reduce the size and power consumption of the non timing-critical portion in the design. We have divided the problem of generating the SOP into three parts: inversion-based creation of the BitClusters (sets of individual partial-product bits, which belong to the ith bitslice), propagation-based reduction of the BitClusters and selective-inversion based computation of the final sum result. Techniques used in these three steps help to reduce the implementation area and power consumption for the SOP block. Our experimental data shows that the SOP block generated by our approach is significantly smaller (8.59% on average) and marginally faster (0.42% on average) than the SOP block generated by a commercially available best-in-class datapath synthesis tool. In addition, our proposed SOP netlist consumes significantly less dynamic power (7.92% on average) and leakage power (5.65% on average) than the netlist generated by the synthesis tool. These improvements were verified on placed-and-routed designs as well.
一种基于反演的面积与功耗高效算术积和综合方法
在最先进的数字信号处理(DSP)和图形应用中,算术乘积和(SOP)是一个重要的计算密集型操作,消耗大量的面积,延迟和功耗。本文提出了一种合成非定时关键SOP块的新算法,该算法可以有效地减少非定时关键部分的尺寸和功耗。我们将生成SOP的问题分为三个部分:基于反转的BitClusters创建(属于第i位片的单个部分积位的集合),基于传播的BitClusters约简以及基于选择性反转的最终和结果计算。在这三个步骤中使用的技术有助于减少SOP块的实现面积和功耗。我们的实验数据表明,与商业上最好的数据路径合成工具生成的SOP块相比,我们的方法生成的SOP块明显更小(平均8.59%),速度略快(平均0.42%)。此外,我们提出的SOP网表消耗的动态功率(平均7.92%)和泄漏功率(平均5.65%)明显低于合成工具生成的网表。这些改进也在放置和路由设计上得到了验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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