Scan Delay Testing of Nanometer SoCs

A. Singh
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引用次数: 3

Abstract

Delay defects that degrade performance and cause timing related reliability failures are emerging to be a major concern in nanometer technologies. Extensive at-speed functional testing to screen out such defects can be prohibitively expensive. Scan based structural delay tests are being pursued as a possible cost effective solution to this problem. However, recent research indicates that several formidable challenges must be overcome before such an approach can be fully effective. These include poor delay test coverage, and inaccuracies in the observed circuit timing due to false paths, power supply noise, clock stretching etc. This tutorial aims at a comprehensive discussion of these challenges and proposed solutions, aided by data from recently published industrial studies from Intel, IBM. TI, Freescale, LSI Logic, and universities.
纳米soc的扫描延迟测试
延迟缺陷会降低性能并导致与时间相关的可靠性故障,这是纳米技术中出现的主要问题。为了筛除这些缺陷而进行的大量高速功能测试可能会非常昂贵。基于扫描的结构延迟测试正在寻求一种可能的经济有效的解决方案来解决这个问题。然而,最近的研究表明,在这种方法能够完全有效之前,必须克服几个艰巨的挑战。这些包括低延迟测试覆盖率,以及由于假路径,电源噪声,时钟拉伸等导致的观察电路时序不准确。本教程旨在全面讨论这些挑战和建议的解决方案,并辅以英特尔、IBM最近发表的工业研究数据。TI,飞思卡尔,LSI逻辑,和大学。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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