21st International Conference on VLSI Design (VLSID 2008)最新文献_第10页

Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit 基于进化虚拟可重构电路的智能天线系统容错动态天线阵列

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.32

D. Dhanasekaran, K. Bagan

{"title":"Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit","authors":"D. Dhanasekaran, K. Bagan","doi":"10.1109/VLSI.2008.32","DOIUrl":"https://doi.org/10.1109/VLSI.2008.32","url":null,"abstract":"A majority of applications require cooperation of two or more independently designed, separately located, but mutually affecting subsystems. In addition to good behavior of each of the subsystems, an effective coordination is very important to achieve the desired overall performance. However, such a co-ordination is very difficult to attain mainly due to the lack of precise system models and/or dynamic parameters. In such situations, the evolvable hardware (EHW) techniques, which can achieve the sophisticated level of information processing the brain is capable of, can excel. In this paper, a new virtual reconfigurable circuit based drive circuit for array elements in smart antenna using the techniques of evolved operators is presented. The idea of this work is to develop a system that is tolerant to array element failure (fault tolerance) by utilizing phased array input programmer connected to a programmable VLSI chip. The approach chosen here is based on functional level evolution whose architecture contains many nonlinear functions and uses an evolutionary algorithm to evolve the best configuration. The system is tested for its effectiveness by choosing a real-time phase control in three element array of smart antenna with three input phases and introducing different element failures such as: element fails as open circuit, sensor fails as short circuit, noise added to individual element, multiple element failure etc.. In each case the mean square error is computed and used as the performance index.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115423170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding 高速Reed-Solomon解码的重新定时分解串行Berlekamp-Massey (BM)架构

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.45

Shahid Rizwan

引用次数: 9

Fast Congestion Aware Routing for Pin Assignment 快速拥塞感知路由引脚分配

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.110

S. Prasad

{"title":"Fast Congestion Aware Routing for Pin Assignment","authors":"S. Prasad","doi":"10.1109/VLSI.2008.110","DOIUrl":"https://doi.org/10.1109/VLSI.2008.110","url":null,"abstract":"Macroblock (aka partition) pin assignment and routing are important tasks in typical top-down hierarchical physical design. Routers use pin locations as connection points to route the design with a goal of minimizing congestion. However, determining suitable pin locations it self depends on availability of congestion free routing topology as a seed input. This results in a catch-22 situation. In this paper, we present an approach, during prototyping phase, to generate fast-and- dirty congestion free routing topology, in top channels. This is real chip routing topology, in the sense that, the routing topology of every net adheres to physical hierarchy, as would happen during hierarchical implementation. This is passed as seed to pin assignment engine, which thus, results in congestion-free pin locations. The novelty of this approach lies in efficient detection of those inter-partition nets whose routing topology have little or no bearing to top channel congestion. These nets are then either not routed or routed in a fast hierarchy unaware manner. We will show that this routing topology is good enough (less than 10% error margin) to establish suitable cross points at partition boundaries, while the speed up achieved is around 6X compared to routing all nets in hierarchy aware manner. Experimental results demonstrate its efficiency and effectiveness. Furthermore, it can also be effectively used as seed input for decisions like channel sizing between partitions, and budgeting timing constraints to partitions.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117094075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures 多核架构中可靠缓存一致性的动态错误检测

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.68

Hui Wang, Sandeep Baldawa, R. Sangireddy

{"title":"Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures","authors":"Hui Wang, Sandeep Baldawa, R. Sangireddy","doi":"10.1109/VLSI.2008.68","DOIUrl":"https://doi.org/10.1109/VLSI.2008.68","url":null,"abstract":"In chip multiprocessor (CMP) systems the various effects of technology scaling make the on chip components more susceptible to faults. Most of the earlier schemes that address fault tolerance issues in CMPs adopt redundant-thread techniques. These techniques are mostly effective, except that they fail to detect errors resulting from faults in hardware components on chip that commonly serve multiple cores. The cache coherence controller (CC) logic, which ensures consistency of data shared among multiple threads, is a vital common component in CMPs. A fault in CC logic of any of the processors may lead to errors in the data states in the entire CMP system. It is observed that up to 59.6% of the memory references cause a change in cache state for SPLASH-2 applications. We propose a novel scheme with a verification logic that can dynamically detect errors in the CC logic of multiple cores in a CMP system. The entire verification logic is designed with a negligible area of 0.1372 sq.mm using a TSMC 0.18 mu4-metal layer process technology. Even at highly aggressive fault injection rates, the logic achieves an average error coverage of more than 95% (and almost 100% for some applications)","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125281016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Variability-Tolerant Register-Transfer Level Synthesis 容变寄存器-传输级合成

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.114

Anish Muttreja, S. Ravi, N. Jha

引用次数: 6

Formal Verification of a Public-Domain DDR2 Controller Design 公共域DDR2控制器设计的形式化验证

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.94

Abhishek Datta, V. Singhal

引用次数: 15

Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers 利用静态学习在CNF SAT求解器中的电路再收敛

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.90

Yinlei Yu, C. Brien, S. Malik

{"title":"Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers","authors":"Yinlei Yu, C. Brien, S. Malik","doi":"10.1109/VLSI.2008.90","DOIUrl":"https://doi.org/10.1109/VLSI.2008.90","url":null,"abstract":"Most contemporary SAT solvers use a conjunctive-normal-form (CNF) representation for logic functions due to the availability of efficient algorithms for this form, such as deduction through unit propagation and conflict driven learning using clause resolution. The use of CNF generally entails transformation to this form from other representations such as logic circuits (Tseitin, 1970). However, this transformation results in loss of information such as direction of signal flow and observability of signals at circuit outputs (Een, 2003)(Fu, 2005). This has prompted the development of various circuit-based solvers (Ganai et al., 2002), hybrid CNF+circuit-based solvers (Fu, 2005), as well as augmented CNF solvers (Een, 2003). Having the circuit available provides for additional capabilities at a cost, and thus requires careful analysis to determine the viability of each approach. This paper highlights one specific capability provided by a circuit: the ability to consider reconvergent paths in unit propagation. Unit propagation is the workhorse of contemporary SAT solvers, thus any improvement to this has significant practical potential. We first demonstrate that the Tseitin circuit-to-CNF transformation limits backward unit propagation and how additional implications can be derived when unit propagation across multiple paths is considered. Next, we show how these implications can be exploited by statically learning clauses during circuit pre-processing. The results of the practical implementation of these algorithms show that the static learning can provide significant speed-up on several classes of benchmark circuits. Finally, we discuss how this work compares with other circuit-based approaches, especially those arising from the automatic-test-pattern-generation (ATPG) community (e.g. recursive learning) and circuit and non- circuit based pre-processors.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124446430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor 统一BCD和二进制加减法器的一种新的超前进位方法

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.80

S. Veeramachaneni, K. M. Krishna, V. PrateekG., S. Subroto, S. Bharat, M. Srinivas

引用次数: 11

Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier 抗功率攻击的高效FPGA倍频器结构

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.65

C. Rebeiro, Debdeep Mukhopadhyay

引用次数: 28

An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies 基于亚微米技术的最优多功能单元动态指令选择逻辑

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.55

Terrell R. Bennett, R. Sangireddy

引用次数: 3