MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks

Abstract

Complex system-on-chip designs targeted for FPGAs merit sophisticated communication architectures to support a host of high performance applications. In this research we implement a hybrid two-layer router architecture for FPGA based NoCs and quantify its area and performance tradeoffs by characterizing a network component library (Mo-Clib). Results from the VHDL and SystemC models of the advanced router architecture show an average improvement of 20.4% in NoC bandwidth (maximum of 24% compared to a traditional NoC). As a part of the CAD flow, we develop an algorithm that utilizes the above NoC framework and includes bandwidth capacity and area as a cost during an automatic NoC topology synthesis phase. Experimental results for a set of real applications and synthetic benchmarks show an average reduction of 21.6% in FPGA area (maximum of 26%) for equivalent bandwidth constraints when compared with a baseline approach.