容变寄存器-传输级合成

Anish Muttreja, S. Ravi, N. Jha
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引用次数: 6

摘要

电路延迟的可变性是数字电路设计和合成中的一个重大挑战。虽然在设计层次的各个层次上都解决了这一挑战,但我们认为可以增强现代寄存器传输层(RTL)合成工具,以另一种有效的方式处理这一问题。我们的解决方案涉及设计可变性容忍,正确的电路假设常见情况,而不是最坏情况下的关键路径延迟值。我们提出了一种设计可变容限电路的方法,该方法可以在运行时检测并有效地从延迟错误中恢复,这将不可避免地由于使用共例延迟值而引入。通过引入影子逻辑来检测并从运行时错误中恢复,可变性不可知设计自动转换为可变性容忍电路,同时利用数据推测来获得性能优势。对于各种基准电路,我们表明我们的方案所施加的面积开销平均仅为11.4%,同时在边际设计中实现高达16.3%的性能加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Variability-Tolerant Register-Transfer Level Synthesis
Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern register-transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.
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