Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding

Shahid Rizwan
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引用次数: 9

Abstract

This paper presents a retimed decomposed inversion-less serial Berlekamp-Massey (BM) architecture for Reed Solomon (RS) decoding. The key idea is to apply the retiming technique into the critical path in order to achieve high decoding performance. The standard basis irregular fully parallel multiplier is separated into partial product generation (PPG) and partial product reduction (PPR) stages to implement the proposed modified decomposed inversion-less serial BM algorithm. The proposed RS (255,239) decoder is implemented in verilog HDL and synthesized with 0.18 mum CMOS std 130 standard cell library. The proposed architecture achieves almost 76 % increase in speed and throughput, and can be used in high-speed and high-throughput applications such as DVD, optical fiber communications, etc.
高速Reed-Solomon解码的重新定时分解串行Berlekamp-Massey (BM)架构
提出了一种用于RS译码的重定时分解无反转串行Berlekamp-Massey (BM)结构。关键思想是将重定时技术应用到关键路径中,以达到较高的解码性能。将标准基不规则全并行乘法器分为部分乘积生成(PPG)和部分乘积约简(PPR)两个阶段,实现改进的分解无反转串行BM算法。所提出的RS(255,239)解码器采用verilog HDL语言实现,并采用0.18 μ m CMOS std 130标准单元库合成。该架构的速度和吞吐量提高了近76%,可用于DVD、光纤通信等高速和高吞吐量应用。
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