基于操作数编码和操作旁路的节能软错误保护

K. Gandhi, N. Mahapatra
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引用次数: 3

摘要

随着设计规模进一步扩大到纳米级,商品产品中的逻辑电路对软错误的脆弱性正在增加,它们对芯片总软错误率(SER)的贡献预计将高达60%,远远超过存储器。我们采用了一种价值感知框架,使组合电路中的操作旁路能够同时降低其中的能耗和SER。与那些在组合逻辑中降低SER的技术不同,这些技术具有非常高的性能和/或能量开销(因为它们通常采用显式的空间或时间冗余),我们的技术通过关闭组合电路的部分来动态地利用操作数值,从而以最小的性能开销减少易受攻击的区域和能量消耗。在整个SPEC CPU2k基准测试套件中,平均而言,我们获得了60%的SER减少和24%的能源节约,对性能的影响最小。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass
As designs scale further into the nanometer regime, the vulnerability of logic circuits in commodity products to soft errors is increasing and their contribution towards total chip soft-error rate (SER) is predicted to be as high as 60%, much more than that of memory. We employ a value-aware framework that enables operation bypass in combinational circuits to simultaneously reduce both energy consumption and SER in them. Unlike techniques that reduce SER in combinational logic with very high performance and/or energy overheads (since they usually employ significant explicit spatial or temporal redundancy), our technique dynamically exploits operand values by shutting off portions of combinational circuits, thus reducing vulnerable area and energy consumption with minimal performance overheads. On the average across the SPEC CPU2k benchmark suite, we obtain 60% SER reduction and 24% energy savings with minimal impact on performance.
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