Formal Verification of a Public-Domain DDR2 Controller Design

Abstract

This paper demonstrates a formal verification- planning process and presents associated verification strategy that we believe is an essential (yet often neglected) step in an ASIC or SoC functional formal verification flow. Our contribution is to present a way to apply the verification planning process and a set of abstraction techniques on a non-trivial open-source example (the Sun OpenSPARCtrade DDR2 controller). The process and verification strategy can be applied to DDR2 controllers in particular and generalized for other designs.