Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier

C. Rebeiro, Debdeep Mukhopadhyay
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引用次数: 28

Abstract

The paper presents an architecture to implement Karatsuba Multiplier on an FPGA platform. Detailed analysis has been carried out on how existing algorithms utilize FPGA resources. Based on the observations the work develops a hybrid technique which has a better area delay product compared to the known algorithms. The results have been practically demonstrated through a large number of experiments. Subsequently, the work develops a masking strategy to prevent power based side channel attacks on the multiplier. It has been found that the proposed masked Hybrid Karatsuba multiplier is more compact compared to existing designs.
抗功率攻击的高效FPGA倍频器结构
本文提出了一种在FPGA平台上实现倍频器的体系结构。详细分析了现有算法如何利用FPGA资源。在此基础上,本文开发了一种混合算法,与已知算法相比,该算法具有更好的面积延迟积。通过大量的实验,结果得到了实际的验证。随后,该工作开发了一种屏蔽策略,以防止对乘法器的基于功率的侧信道攻击。研究发现,与现有设计相比,所提出的掩膜混合卡拉suba乘法器更加紧凑。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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