A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor

S. Veeramachaneni, K. M. Krishna, V. PrateekG., S. Subroto, S. Bharat, M. Srinivas
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引用次数: 11

Abstract

Increasing prominence of commercial, financial and Internet-based applications, which process decimal data, there is an increasing interest in providing hardware support for such data. In this paper, new architecture for efficient binary and binary coded decimal (BCD) adder/subtracter is presented. This employs a new method of subtraction unlike the existing designs which mostly use 10's complements, to obtain a much lower latency. Though there is a necessity of correction in some cases, the delay overhead is minimal. A complete discussion about such cases and the required logic to process is presented. The architecture is run-time reconfigurable to facilitate both BCD and binary operations, including signed and unsigned numbers. The proposed circuits are compared (both qualitatively as well as quantitatively) with the existing circuits in literature and are shown to perform better. Simulation results show that the proposed architecture is at least 11% faster than the existing designs.
统一BCD和二进制加减法器的一种新的超前进位方法
处理十进制数据的商业、金融和基于internet的应用程序日益突出,因此对为此类数据提供硬件支持的兴趣日益增加。本文提出了一种高效二进制和二进制编码十进制(BCD)加/减法器的新结构。这采用了一种新的减法方法,不像现有的设计,主要使用10的补数,以获得更低的延迟。虽然在某些情况下需要进行校正,但延迟开销是最小的。对这种情况和处理所需的逻辑进行了完整的讨论。该体系结构在运行时可重新配置,以促进BCD和二进制操作,包括有符号数和无符号数。将所提出的电路与文献中现有的电路进行了定性和定量的比较,并显示出更好的性能。仿真结果表明,所提架构比现有设计至少快11%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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