Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures

Hui Wang, Sandeep Baldawa, R. Sangireddy
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引用次数: 20

Abstract

In chip multiprocessor (CMP) systems the various effects of technology scaling make the on chip components more susceptible to faults. Most of the earlier schemes that address fault tolerance issues in CMPs adopt redundant-thread techniques. These techniques are mostly effective, except that they fail to detect errors resulting from faults in hardware components on chip that commonly serve multiple cores. The cache coherence controller (CC) logic, which ensures consistency of data shared among multiple threads, is a vital common component in CMPs. A fault in CC logic of any of the processors may lead to errors in the data states in the entire CMP system. It is observed that up to 59.6% of the memory references cause a change in cache state for SPLASH-2 applications. We propose a novel scheme with a verification logic that can dynamically detect errors in the CC logic of multiple cores in a CMP system. The entire verification logic is designed with a negligible area of 0.1372 sq.mm using a TSMC 0.18 mu4-metal layer process technology. Even at highly aggressive fault injection rates, the logic achieves an average error coverage of more than 95% (and almost 100% for some applications)
多核架构中可靠缓存一致性的动态错误检测
在芯片多处理器(CMP)系统中,技术缩放的各种影响使芯片上的组件更容易发生故障。大多数解决cmp中容错问题的早期方案都采用冗余线程技术。这些技术大多是有效的,除了它们无法检测到通常服务于多个核心的芯片上的硬件组件故障所导致的错误。缓存一致性控制器(CC)逻辑是cmp中重要的公共组件,它保证了多线程间共享数据的一致性。任何处理器的CC逻辑出现故障都可能导致整个CMP系统的数据状态出现错误。可以观察到,高达59.6%的内存引用会导致SPLASH-2应用程序的缓存状态发生变化。我们提出了一种新的验证逻辑方案,该方案可以动态检测CMP系统中多核CC逻辑中的错误。整个验证逻辑的设计面积为0.1372平方,可以忽略不计。mm采用台积电0.18 mu4金属层工艺技术。即使在高度激进的故障注入率下,逻辑也能实现95%以上的平均错误覆盖率(对于某些应用程序几乎是100%)。
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