Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding

This paper presents a retimed decomposed inversion-less serial Berlekamp-Massey (BM) architecture for Reed Solomon (RS) decoding. The key idea is to apply the retiming technique into the critical path in order to achieve high decoding performance. The standard basis irregular fully parallel multiplier is separated into partial product generation (PPG) and partial product reduction (PPR) stages to implement the proposed modified decomposed inversion-less serial BM algorithm. The proposed RS (255,239) decoder is implemented in verilog HDL and synthesized with 0.18 mum CMOS std 130 standard cell library. The proposed architecture achieves almost 76 % increase in speed and throughput, and can be used in high-speed and high-throughput applications such as DVD, optical fiber communications, etc.