存储器设计与先进半导体技术

D. Harame, S. Iyer, J. Watts, R. Joshi, J. Barth
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引用次数: 0

摘要

本教程将提供一个自底向上的视角,随着我们进入纳米时代,半导体存储器设计的变化。我们首先讨论缩放的分解和功率问题。随着创新取代传统的缩放,我们研究了应力工程的使用来提高器件级性能。解决了光刻和互连方面的技术挑战。还必须考虑创新和缩放对RF/模拟特性的影响。内存的扩展是另一个挑战。我们将继续为电路设计者讨论这些影响的建模,包括讨论许多新的和传统的变化源。我们描述了这些是如何表征的,如何通过布局规则控制它们,以及如何在模型中描述剩余的变化以启用统计时序和其他高级电路技术。在电路层面,我们详细考虑了嵌入式DRAM和SRAM的设计,包括批量和SOI。我们讨论了先进技术的好处和挑战,包括在制造变化的存在下创建稳健设计的方法。我们还讨论了利用先进技术克服“内存墙”、“功率墙”和“ILP墙”所需的设计创新。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Memory Design and Advanced Semiconductor Technology
This tutorial will provide a bottom-up view of the changes in semiconductor memory design as we move into the nanometer regime. We begin by discussing the breakdown of scaling and the power problem. As innovation replaces classical scaling we investigate the use of stress engineering to improve device level performance. Technology challenges in lithography and interconnects are addressed. The consequences of innovation and scaling on RF/Analog characteristics must also be considered. The scaling of memory presents yet another challenge. We proceed to discuss the modeling of these effects for the circuit designer including discussion of the many new and traditional sources of variation. We describe how these are characterized how they can be controlled by layout rules and how the remaining variation can be describe in the model to enable Statistical Timing and other advanced circuit techniques. At the circuit level we consider in detail embedded DRAM and SRAM design for both bulk and SOI. We discuss the benefits and challenges of advanced technologies including methods for creating robust designs in the presence of manufacturing variation. We also discuss the design innovations required to utilize advanced technologies for overcoming the "memory wall", "power wall" and "ILP wall".
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