{"title":"Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I Converters","authors":"S. Garimella","doi":"10.1109/VLSI.2008.91","DOIUrl":null,"url":null,"abstract":"A novel compact four quadrant CMOS transconductance analog multiplier with wide dynamic swing and wide gain bandwidth product using source- degeneration V-I converters is proposed. The design consists of two stages. First stage is a voltage adder and utilizes two V-I converters with diode connected load and source-degeneration resistor which can provide high bandwidth. The second stage consists of two cross connected differential pairs with source- degeneration resistor which act as current steering elements performing V to I conversion with wide dynamic swing and continuous adjustable gain. Unlike conventional multipliers, in the proposed scheme all the significant intermediate terms generated are linear reducing the non-linear term cancellation, making the circuit power efficient. SPICE simulation results in 0.5 mum CMOS AMI technology are presented which validate the proposed work.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st International Conference on VLSI Design (VLSID 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI.2008.91","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A novel compact four quadrant CMOS transconductance analog multiplier with wide dynamic swing and wide gain bandwidth product using source- degeneration V-I converters is proposed. The design consists of two stages. First stage is a voltage adder and utilizes two V-I converters with diode connected load and source-degeneration resistor which can provide high bandwidth. The second stage consists of two cross connected differential pairs with source- degeneration resistor which act as current steering elements performing V to I conversion with wide dynamic swing and continuous adjustable gain. Unlike conventional multipliers, in the proposed scheme all the significant intermediate terms generated are linear reducing the non-linear term cancellation, making the circuit power efficient. SPICE simulation results in 0.5 mum CMOS AMI technology are presented which validate the proposed work.
提出了一种新型的紧凑的四象限CMOS跨导模拟乘法器,具有宽动态摆幅和宽增益带宽积。设计分为两个阶段。第一级是电压加法器,利用两个V-I转换器,二极管连接负载和源退化电阻,可以提供高带宽。第二级由两个带源退化电阻的交叉连接的差分对组成,它们作为电流转向元件进行V到I转换,具有宽动态摆动和连续可调增益。与传统乘法器不同的是,该方案中产生的所有重要中间项都是线性的,减少了非线性项的抵消,从而提高了电路的功率效率。给出了在0.5 μ m CMOS AMI技术上的SPICE仿真结果,验证了所提出的工作。