100MHz至1GHz, 0.35V至1.5V供应256 x 64 SRAM块,使用对称的9T SRAM单元与控制读取

Satish Anand Verkila, Sivakumar Bondada, B. Amrutur
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引用次数: 28

摘要

在本文中,我们提出了动态电压和频率管理的256 x 64 SRAM块在65纳米技术,频率范围从100 MHz到1 GHz。在上述范围内的任何工作频率下,总能量最小,待机模式下泄漏能量最小。由于SRAM电池的噪声裕度在低电压下恶化,我们提出了静态噪声裕度改善电路,该电路通过控制下拉NMOS晶体管的体偏置来使SRAM电池对称。我们使用9T SRAM单元,隔离读取和保持噪声裕度,泄漏更少。我们实现了一种有效的将地址解码器在待机模式下推入之字形超截止的技术,而不影响其在主动工作模式下的性能。控制读位线(RBL)电压降,仅在需要时才对位线进行预充电,以减少功率浪费。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read
In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose static noise margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and hold noise margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag- super-cut-off in stand-by mode without affecting its performance in active mode of operation. The read bit line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.
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