0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops

B. Srinivasan, V. Chandratre, Menka Tewani
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引用次数: 8

Abstract

This paper describes the architecture and performance of a 0.35 mu, 1 GHZ, CMOS timing generator using array of delay lock loop. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub gate delay resolution to be implemented. The proposed delay lock loops uses novel multiplexer based dual phase and frequency detector along with a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge and the trailing edge of an input clock reference. This greatly reduces the timing jitter, loop locks to both the leading and trailing clock edges as the dual phase and frequency detector along with charge pump converts the phase difference in to voltages. Test results show a timing jitter of less than 20 pS for the DLL (delay lock loop) circuit .The DLL has a dead zone less than 0.01 nS in the phase characteristics and has low phase sensitivity errors. The timing generator is implemented as an array of delay locked loops (Kostamovaara, 2000) which exponentially reduce the locking time. An experimental proto type was simulated at 0.7 mu and 0.35 mu technologies with a supply voltage of 5 V and 3.3 V respectively.
0.35µ,1 GHz,采用数字延时锁环阵列的CMOS时序发生器
本文介绍了一种0.35亩、1 GHZ CMOS延时锁相环阵列定时发生器的结构和性能。时序发生器被实现为一组延迟锁定环路。该架构使具有子门延迟分辨率的时序发生器得以实现。所提出的延时锁环采用一种新型的基于多路复用器的双相位和频率检测器以及电荷泵,当环路接近输入时钟基准的前后边缘锁定时,注入的电荷趋于零。这大大减少了时序抖动,当双相位和频率检测器以及电荷泵将相位差转换为电压时,环路锁定到前后时钟边缘。测试结果表明,延时锁相电路的时序抖动小于20ps,相位特性死区小于0.01 nS,相敏误差较小。时序发生器被实现为一组延迟锁定环路(Kostamovaara, 2000),以指数方式减少锁定时间。实验样机分别在0.7亩和0.35亩的技术条件下,在5 V和3.3 V的电源电压下进行模拟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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