使用像素截断的VBSME低功耗硬件架构

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI:10.1109/VLSI.2008.100

A. Bahari, T. Arslan, A. Erdogan

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引用次数: 6

摘要

本文提出了一种利用全搜索实现低功耗可变块大小运动估计的有效架构。通过分两步执行搜索来实现功耗降低:低像素分辨率和全像素分辨率。我们分析了支持这两种搜索模式所需的计算和存储单元。与传统建筑相比，拟议的建筑减少了50%的总能耗，增加了6%的面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low Power Hardware Architecture for VBSME Using Pixel Truncation

This paper presents an efficient architecture to implement low power variable block size motion estimation (VBSME) using full search. Power reduction is achieved by performing the search in two steps: low pixel resolution and full pixel resolution. We analysed the computation and memory units needed to support these two search modes. The proposed architecture reduces the total energy consumption by 50% with 6% additional area compared to the conventional architecture.

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21st International Conference on VLSI Design (VLSID 2008)

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