Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

Abstract

In this paper analytical expressions for optimal V_dd and V_th to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal V_dd and V_th is analyzed. A new gradient based algorithm for controlling V_dd and V_th based on delay and power monitoring results is proposed. A V_dd-V_th controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.