21st International Conference on VLSI Design (VLSID 2008)最新文献_第7页

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization 基于堆栈的电压和温度可扩展标准电池泄漏模型的统计泄漏表征

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.38

Janakiraman Viraraghavan, B. P. Das, B. Amrutur

{"title":"Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization","authors":"Janakiraman Viraraghavan, B. P. Das, B. Amrutur","doi":"10.1109/VLSI.2008.38","DOIUrl":"https://doi.org/10.1109/VLSI.2008.38","url":null,"abstract":"With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129812178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design 减少互补动态和差分逻辑:一种CMOS逻辑风格的抗dpa安全IC设计

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.77

S. Rammohan, V. Sundaresan, R. Vemuri

{"title":"Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design","authors":"S. Rammohan, V. Sundaresan, R. Vemuri","doi":"10.1109/VLSI.2008.77","DOIUrl":"https://doi.org/10.1109/VLSI.2008.77","url":null,"abstract":"In recent years, Differential Power Analysis (DPA) attack has become a major threat to the security of embedded cryptographic ICs (secure ICs) like smart cards. DPA attack is a powerful side-channel attack. During a DPA attack, the attacker uses power consumption measurements from the secure IC and statistical techniques to correlate the power consumption information leaked with the secret key stored in the secure IC, thus retrieving the secret key, and effectively breaking the secure IC. In this paper, we present a Reduced Complementary Dynamic and Differential Logic (RCDDL) style to design DPA-resistant, secure ICs. RCDDL style ensures that the power consumption of the secure IC remains invariant, and hence, uncorrelated to the input data (secret key). As opposed to existing DDL styles that complement every gate in the uncomplementary logic to generate the differential output, RCDDL style proposes reuse of gates, thus ensuring that a reduced number of gates in the uncomplementary logic are complemented to generate the differential output. Further, we present an analysis of how reduced complementation is achieved while maintaining the capacitance and switching requirements for power invariance. To evaluate the proposed logic style, we built a set of logic gates typically used to design secure ICs. Experiments on a set of circuits, designed using the set of RCDDL gates, show significant improvements in security strength, power consumption and area.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121523106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair 双CMOS对数字可调谐Gm-C滤波器的VLSI实现

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.39

S. Ramasamy, B. Venkataramani, K. Anbugeetha

引用次数: 4

An Optical Reconfiguration System with Four Contexts 具有四种背景的光学重构系统

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.27

N. Yamaguchi, Minoru Watanabe

引用次数: 0

Energy Reduction in SRAM using Dynamic Voltage and Frequency Management 使用动态电压和频率管理降低SRAM的能量

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.47

I. MohammedShareef, P. Nair, B. Amrutur

引用次数: 2

Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples 基于样条中心和自适应样本范围回归的失配感知模拟性能宏建模

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.76

Shubhankar Basu, Balaji Kommineni, R. Vemuri

引用次数: 2

Design Automation Standards: The IP Providers Perspective 设计自动化标准:IP提供商视角

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.140

J. Goodenough

引用次数: 0

Programming and Performance Modelling of Automotive ECU Networks 汽车ECU网络的编程与性能建模

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.131

S. Chakraborty, S. Ramesh

{"title":"Programming and Performance Modelling of Automotive ECU Networks","authors":"S. Chakraborty, S. Ramesh","doi":"10.1109/VLSI.2008.131","DOIUrl":"https://doi.org/10.1109/VLSI.2008.131","url":null,"abstract":"The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementations of different functionalities. Today, in high-end cars, it is common to have around 70 electronic control units (ECUs), each consisting of programmable processors, one or more microcontrollers and a set of sensors and actuators. Different functionalities (e.g. adaptive cruise control or anti-lock braking) are then implemented in a distributed fashion with parts of a task being mapped onto one or more ECUs and these ECUs exchanging messages and signals via high-speed communication buses. The heterogeneity and the distributed nature of these implementations, coupled with the emergence of new standards and protocols for the automotive domain have given rise to new challenges - both in terms of programming large-scale ECU networks, as well as in evaluating their performance and timing properties. This tutorial will provide a comprehensive overview of the recent developments in this domain and also highlight some of the challenges facing embedded systems designers and programmers. The topics covered will include time-triggered architectures for implementing safety-critical applications, emerging protocols for the automotive domain such as FlexRay, techniques for performance and timing analysis of FlexRay-based ECU networks, and languages and tools for developing distributed implementations of automotive functionality around FlexRay and other related protocols. Apart from discussing the relevant protocols, languages and modelling/analysis techniques, the tutorial will also cover practical case studies and some commercially available tools and their functionality.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115491182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits 基于二极管-电阻器的纳米级横向PLA电路分析与稳健设计

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.44

R. Chakraborty, Somnath Paul, S. Bhunia

{"title":"Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits","authors":"R. Chakraborty, Somnath Paul, S. Bhunia","doi":"10.1109/VLSI.2008.44","DOIUrl":"https://doi.org/10.1109/VLSI.2008.44","url":null,"abstract":"Logic circuit design with future nanoscale devices using dense and regular fabrics such as crossbar is promising in terms of integration density, performance and power dissipation. Among the emerging alternatives to CMOS, molecular electronics based \"diode-resistor logic\" has generated considerable interest in recent times. However, some major challenges associated with circuit design using molecular switches are: 1) high defect rate; 2) lack of voltage gain of these switches that prevent logic cascading; and 3) large output voltage level degradation that affect robustness of operation. In this paper, we analyze the issue of input-dependent logic level degradation in diode-resistor style molecular crossbar and develop a simple analytical model for fast and accurate estimation of logic level degradation in a circuit. We also propose a voltage level-aware circuit design technique that limits the worst-case output level degradation. We verify the model by SPICE simulation which shows an average absolute error of less than 2%. Moreover, the proposed design technique improves the logic degradation level from 27% to 7% on an average compared to conventional design.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122466464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Temperature and Process Variations Aware Power Gating of Functional Units 功能单元的温度和工艺变化感知功率门控

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.83

D. Kannan, Aviral Shrivastava, V. Mohan, Sarvesh Bhardwaj, S. Vrudhula

引用次数: 16