基于二极管-电阻器的纳米级横向PLA电路分析与稳健设计

R. Chakraborty, Somnath Paul, S. Bhunia
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引用次数: 3

摘要

在集成密度、性能和功耗方面,未来纳米级器件的逻辑电路设计采用密集和规则的织物,如横杆。在新兴的CMOS替代品中,基于分子电子学的“二极管-电阻逻辑”近年来引起了相当大的兴趣。然而,与使用分子开关的电路设计相关的一些主要挑战是:1)高缺陷率;2)这些开关缺乏防止逻辑级联的电压增益;3)输出电压电平下降大,影响运行稳健性。本文分析了二极管-电阻式分子交联中与输入相关的逻辑电平退化问题,并建立了一个简单的分析模型,用于快速准确地估计电路中的逻辑电平退化。我们还提出了一种电压电平感知电路设计技术,以限制最坏情况下的输出电平退化。通过SPICE仿真验证了该模型的正确性,平均绝对误差小于2%。此外,与传统设计相比,所提出的设计技术将逻辑退化水平平均从27%提高到7%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits
Logic circuit design with future nanoscale devices using dense and regular fabrics such as crossbar is promising in terms of integration density, performance and power dissipation. Among the emerging alternatives to CMOS, molecular electronics based "diode-resistor logic" has generated considerable interest in recent times. However, some major challenges associated with circuit design using molecular switches are: 1) high defect rate; 2) lack of voltage gain of these switches that prevent logic cascading; and 3) large output voltage level degradation that affect robustness of operation. In this paper, we analyze the issue of input-dependent logic level degradation in diode-resistor style molecular crossbar and develop a simple analytical model for fast and accurate estimation of logic level degradation in a circuit. We also propose a voltage level-aware circuit design technique that limits the worst-case output level degradation. We verify the model by SPICE simulation which shows an average absolute error of less than 2%. Moreover, the proposed design technique improves the logic degradation level from 27% to 7% on an average compared to conventional design.
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