{"title":"基于二极管-电阻器的纳米级横向PLA电路分析与稳健设计","authors":"R. Chakraborty, Somnath Paul, S. Bhunia","doi":"10.1109/VLSI.2008.44","DOIUrl":null,"url":null,"abstract":"Logic circuit design with future nanoscale devices using dense and regular fabrics such as crossbar is promising in terms of integration density, performance and power dissipation. Among the emerging alternatives to CMOS, molecular electronics based \"diode-resistor logic\" has generated considerable interest in recent times. However, some major challenges associated with circuit design using molecular switches are: 1) high defect rate; 2) lack of voltage gain of these switches that prevent logic cascading; and 3) large output voltage level degradation that affect robustness of operation. In this paper, we analyze the issue of input-dependent logic level degradation in diode-resistor style molecular crossbar and develop a simple analytical model for fast and accurate estimation of logic level degradation in a circuit. We also propose a voltage level-aware circuit design technique that limits the worst-case output level degradation. We verify the model by SPICE simulation which shows an average absolute error of less than 2%. Moreover, the proposed design technique improves the logic degradation level from 27% to 7% on an average compared to conventional design.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits\",\"authors\":\"R. Chakraborty, Somnath Paul, S. Bhunia\",\"doi\":\"10.1109/VLSI.2008.44\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Logic circuit design with future nanoscale devices using dense and regular fabrics such as crossbar is promising in terms of integration density, performance and power dissipation. Among the emerging alternatives to CMOS, molecular electronics based \\\"diode-resistor logic\\\" has generated considerable interest in recent times. However, some major challenges associated with circuit design using molecular switches are: 1) high defect rate; 2) lack of voltage gain of these switches that prevent logic cascading; and 3) large output voltage level degradation that affect robustness of operation. In this paper, we analyze the issue of input-dependent logic level degradation in diode-resistor style molecular crossbar and develop a simple analytical model for fast and accurate estimation of logic level degradation in a circuit. We also propose a voltage level-aware circuit design technique that limits the worst-case output level degradation. We verify the model by SPICE simulation which shows an average absolute error of less than 2%. Moreover, the proposed design technique improves the logic degradation level from 27% to 7% on an average compared to conventional design.\",\"PeriodicalId\":143886,\"journal\":{\"name\":\"21st International Conference on VLSI Design (VLSID 2008)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"21st International Conference on VLSI Design (VLSID 2008)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI.2008.44\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st International Conference on VLSI Design (VLSID 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI.2008.44","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits
Logic circuit design with future nanoscale devices using dense and regular fabrics such as crossbar is promising in terms of integration density, performance and power dissipation. Among the emerging alternatives to CMOS, molecular electronics based "diode-resistor logic" has generated considerable interest in recent times. However, some major challenges associated with circuit design using molecular switches are: 1) high defect rate; 2) lack of voltage gain of these switches that prevent logic cascading; and 3) large output voltage level degradation that affect robustness of operation. In this paper, we analyze the issue of input-dependent logic level degradation in diode-resistor style molecular crossbar and develop a simple analytical model for fast and accurate estimation of logic level degradation in a circuit. We also propose a voltage level-aware circuit design technique that limits the worst-case output level degradation. We verify the model by SPICE simulation which shows an average absolute error of less than 2%. Moreover, the proposed design technique improves the logic degradation level from 27% to 7% on an average compared to conventional design.