基于统一Vdd Vth优化的逻辑块DVFM控制器

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI:10.1109/VLSI.2008.69

S. Kannan, N. S. Sreeram, B. Amrutur

{"title":"基于统一Vdd Vth优化的逻辑块DVFM控制器","authors":"S. Kannan, N. S. Sreeram, B. Amrutur","doi":"10.1109/VLSI.2008.69","DOIUrl":null,"url":null,"abstract":"In this paper analytical expressions for optimal Vdd and Vth to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal Vdd and Vth is analyzed. A new gradient based algorithm for controlling Vdd and Vth based on delay and power monitoring results is proposed. A Vdd-Vth controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block\",\"authors\":\"S. Kannan, N. S. Sreeram, B. Amrutur\",\"doi\":\"10.1109/VLSI.2008.69\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper analytical expressions for optimal Vdd and Vth to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal Vdd and Vth is analyzed. A new gradient based algorithm for controlling Vdd and Vth based on delay and power monitoring results is proposed. A Vdd-Vth controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.\",\"PeriodicalId\":143886,\"journal\":{\"name\":\"21st International Conference on VLSI Design (VLSID 2008)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"21st International Conference on VLSI Design (VLSID 2008)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI.2008.69\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st International Conference on VLSI Design (VLSID 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI.2008.69","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文导出了给定速度约束下能量最小的最优Vdd和Vth的解析表达式。这些表达式基于晶体管的EKV模型，在强反转和亚阈值区域都有效。分析了栅极泄漏对最优Vdd和Vth的影响。提出了一种基于时延和功率监测结果的梯度控制Vdd和Vth的新算法。设计了一个Vdd-Vth控制器，利用该算法对典型逻辑块(MPEG解码器的绝对差分计算和)的电源和阈值电压进行动态控制。给出了采用65nm预测技术模型的仿真结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

In this paper analytical expressions for optimal V_dd and V_th to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal V_dd and V_th is analyzed. A new gradient based algorithm for controlling V_dd and V_th based on delay and power monitoring results is proposed. A V_dd-V_th controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.

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21st International Conference on VLSI Design (VLSID 2008)

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