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2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)最新文献

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Composite Resistor Technique for Process and Temperature Compensations of Low Power Ring Oscillators 低功率环形振荡器工艺和温度补偿的复合电阻技术
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-03-18 DOI: 10.1109/LASCAS.2019.8667567
H. Çetinkaya, A. Zeki, Alper Girgin, T. Karalar
{"title":"Composite Resistor Technique for Process and Temperature Compensations of Low Power Ring Oscillators","authors":"H. Çetinkaya, A. Zeki, Alper Girgin, T. Karalar","doi":"10.1109/LASCAS.2019.8667567","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667567","url":null,"abstract":"A process and temperature compensation technique, namely, composite resistor, is adopted for the current controlled oscillators (CCOs). The core is a ring oscillator (RO) and oscillates at 1 MHz at room temperature (25°C) with 50% duty cycle. The temperature compensation is achieved between -20°C and 100°C, and after trimming, the inaccuracies of the output frequencies, 1 MHz, and 0.5 MHz, are below ±1% (3σ) in the same temperature range. As a result, 2 outputs are temperature compensated. The oscillator core consumes 750 nA, the biasing circuit consumes 360 nA, and the complete system consumes 1.256 μA, corresponding to 2 μW at 1.6 V battery voltage. The design, occupying 130 μm × 285 μm die area, is realized in a 0.18 μm Mixed-Signal RF Salicide (1P6M, 1.8V/3.3V) CMOS process.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124676903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low Noise Front-End and ADC for Real-Time ECG System in CMOS Process CMOS工艺下实时心电系统的低噪声前端和ADC
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-03-14 DOI: 10.1109/LASCAS.2019.8667551
Pablo J. Gardella, Villa Fernandez Emanuel, B. Eduardo, Biberidis Nicolas, M. Juan
{"title":"Low Noise Front-End and ADC for Real-Time ECG System in CMOS Process","authors":"Pablo J. Gardella, Villa Fernandez Emanuel, B. Eduardo, Biberidis Nicolas, M. Juan","doi":"10.1109/LASCAS.2019.8667551","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667551","url":null,"abstract":"This paper presents the design and experimental results of a digital acquisition system based on a chopper-stabilized Instrumentation Amplifier with Common-Mode feedback for CMRR enhancement. Chopping techniques are used to remove both offset and flicker noise, detrimental effects characteristic of pure CMOS processes. A second-order, discrete-time, single-bit Sigma-Delta ADC with CIFB structure is used to convert the signal into the digital domain where it can be processed in real time to diagnose and report urgencies. Measurements on a 0.6μm process have shown that the input CMRR is boosted by 71dB when the feedback is closed through the patient. The input referred integrated noise for the overall system within the ECG band frequencies of 0.1Hz to 400Hz (including the quantization noise) is 4.2μVP, below the recommended maximum detection error of 10.0μVP.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121073281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
LIM Algorithms for MOSFET Models MOSFET模型的LIM算法
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-03-14 DOI: 10.1109/LASCAS.2019.8667600
J. Schutt-Ainé, P. Goh
{"title":"LIM Algorithms for MOSFET Models","authors":"J. Schutt-Ainé, P. Goh","doi":"10.1109/LASCAS.2019.8667600","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667600","url":null,"abstract":"This paper introduces algorithms for the simulation of MOSFETS using the latency insertion method (LIM). The algorithms are independent of the MOSFET model level chosen and account for current and charge effects. The latency insertion method (LIM) has been demonstrated as an optimum algorithm for the transient simulation of large networks. In particular, we address the generation of the update equations. Examples and comparisons are given for evaluating the algorithms.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114912662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Microprocessor Design with a Direct Bluetooth Connection in 45 nm Technology Using Microwind 使用Microwind的45纳米技术直接蓝牙连接的微处理器设计
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-24 DOI: 10.1109/LASCAS.2019.8667540
Esteban Garzón, Felix Chavez, Diego Jaramillo, Luis Sanchez, Sofia Lara, Carlos Macias, E. Acurio, L. Prócel, L. Trojman, E. Sicard
{"title":"Microprocessor Design with a Direct Bluetooth Connection in 45 nm Technology Using Microwind","authors":"Esteban Garzón, Felix Chavez, Diego Jaramillo, Luis Sanchez, Sofia Lara, Carlos Macias, E. Acurio, L. Prócel, L. Trojman, E. Sicard","doi":"10.1109/LASCAS.2019.8667540","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667540","url":null,"abstract":"This paper presents the full-custom design of a 45 nm microprocessor using the electronic design automation (EDA) software, Microwind. The design consists of fundamental modules: the arithmetic logic unit (ALU), memory, counter and an integrated Bluetooth (BT) port working at the 2.4 GHz. This design is validated by simulation under a process, voltage, and temperature (PVT) testing. The microprocessor can handle up to 4 bit since its purpose is focused on specific applications such as the internet of things (IoT). In order to communicate to the external world and with other devices, a strong input/output data interface and radio frequency (RF) transmission modules are implemented. Moreover, the RF module also contains a Bluetooth communication, which allows the wireless data transmission from/to the microprocessor.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124022628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Prototyping a Biologically Plausible Neuron Model on a Heterogeneous CPU-FPGA Board 在异构CPU-FPGA板上建立生物学上可信的神经元模型
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667538
Kaleb Alfaro-Badilla, A. Chacón-Rodríguez, Georgios Smaragdos, C. Strydis, Andrés Arroyo-Romero, Javier Espinoza-González, C. Salazar-García
{"title":"Prototyping a Biologically Plausible Neuron Model on a Heterogeneous CPU-FPGA Board","authors":"Kaleb Alfaro-Badilla, A. Chacón-Rodríguez, Georgios Smaragdos, C. Strydis, Andrés Arroyo-Romero, Javier Espinoza-González, C. Salazar-García","doi":"10.1109/LASCAS.2019.8667538","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667538","url":null,"abstract":"A heterogeneous hardware-software system implemented on an Avnet ZedBoard Zynq SoC platform, is proposed for the computation of an extended Hodgkin Huxley (eHH), biologically plausible neural model. SoC’s ARM A9 is in charge of handling execution of a single neuron as defined in the eHH model, each with a O(N) computational complexity, while the computation of the gap-junctions interactions for each cell is offloaded on the SoC’s FPGA, cutting its O(N2) complexity by exploiting parallel-computing hardware techniques. The proposed hw-sw solution allows for speed-ups of about 18 times visa-vis à vectorized software implementation on the SoC’s cores, and is comparable to the speed of the same model optimized for a 64-bit Intel Quad Core i7, at 3.9GHz.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"304 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115250935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
LASCAS 2019 Author Index LASCAS 2019作者索引
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/lascas.2019.8667602
{"title":"LASCAS 2019 Author Index","authors":"","doi":"10.1109/lascas.2019.8667602","DOIUrl":"https://doi.org/10.1109/lascas.2019.8667602","url":null,"abstract":"","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128039007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Very Compact CMOS Analog Multiplier for Application in CNN Synapses 一种用于CNN突触的非常紧凑的CMOS模拟乘法器
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667594
Antonio José Sobrinho de Sousa, F. Cardoso, Kelvin Kefren Carvalho Feitosa Nunes, F. Andrade, Gabriele Costa Goncalves, E. Santana, A. Cunha
{"title":"A Very Compact CMOS Analog Multiplier for Application in CNN Synapses","authors":"Antonio José Sobrinho de Sousa, F. Cardoso, Kelvin Kefren Carvalho Feitosa Nunes, F. Andrade, Gabriele Costa Goncalves, E. Santana, A. Cunha","doi":"10.1109/LASCAS.2019.8667594","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667594","url":null,"abstract":"This work presents a CMOS analog multiplier architecture for application as the synapse in analog cellular neural networks. The circuit comprises two voltage-mode inputs and a current-mode output. Simulated performance features obtained from a circuit design in CMOS 130 nm technology include: +100 mV input voltage range, 23 µW static power, −32 dB maximum total harmonic distortion and −3 dB bandwidth of 51.2 kHz. The active area totalizes only 40 µm2.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128117050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Process Variability Challenges for Radiation Mitigation Techniques on 16nm 工艺可变性对16nm辐射减缓技术的挑战
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667575
S. P. Toledo, R. Reis, C. Meinhardt
{"title":"Process Variability Challenges for Radiation Mitigation Techniques on 16nm","authors":"S. P. Toledo, R. Reis, C. Meinhardt","doi":"10.1109/LASCAS.2019.8667575","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667575","url":null,"abstract":"This paper investigates the impact of process variability on traditional radiation and noise mitigation techniques for deep nanometer bulk CMOS technologies. Schmitt Trigger, Strengthening, Pseudo-Strengthening, and Rad-Hard techniques are explored observing the sensitivity to process variability. Results show that these techniques operating under process variability can introduce substantial degradation on timing and power. This study presents the benefits, and the drawbacks brought from the applied methods.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134348730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Ultra-Low Power Multi-Level Power-on Reset for Fine-Grained Power Management Strategies 面向细粒度电源管理策略的超低功耗多级上电复位
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667574
G. LuisE.Rueda, Nestor Cuevas, E. Roa
{"title":"An Ultra-Low Power Multi-Level Power-on Reset for Fine-Grained Power Management Strategies","authors":"G. LuisE.Rueda, Nestor Cuevas, E. Roa","doi":"10.1109/LASCAS.2019.8667574","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667574","url":null,"abstract":"This paper proposes a multi-level POR circuit with programmable voltage thresholds, that can operate in different fine-grained power management strategies. The POR is designed in a 0.18µm standard-logic CMOS technology, and occupies an area of 110µm x 70µm. Simulations results show a robust performance over process and temperature variations (PVT), rising times ranging from 1µs to 1s, and different supply values, while consuming a current of 19nA.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132143863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 13-nW Voltage Reference with Orthogonal Trimming of Absolute Value and Temperature Coefficient 一种13-nW的绝对值和温度系数正交校正电压基准
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667569
J. A. Lima, F. Dualibe
{"title":"A 13-nW Voltage Reference with Orthogonal Trimming of Absolute Value and Temperature Coefficient","authors":"J. A. Lima, F. Dualibe","doi":"10.1109/LASCAS.2019.8667569","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667569","url":null,"abstract":"An all-MOSFET voltage reference generator (VRG) with innovative trimming that orthogonally adjusts V<inf>REF</inf> and temperature coefficient (TC) has been designed in 0.18μm CMOS process. The circuit works from V<inf>DD</inf> = 0.5V, featuring V<inf>REF</inf>=239.9mV and TC =14.6ppm/°C. SPICE data reveal, for 0.5V ≤ VDD ≤ 1.5V, -40°C ≤ T ≤ 120°C and over all corners, post-trimming maximum spread of 1.63% and 34.5ppm/°C, respectively for ΔV<inf>REF</inf>/V<inf>REF</inf> and TC. Typically, consumption is only 13nW@120°C. Line regulation of 0.21%/V and rejection to supply-line noise of 115.5dB@100MHz are also predicted. Monte Carlo reveals post-trim 0.9% (3σ) accurate VREF.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132441052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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