Low Noise Front-End and ADC for Real-Time ECG System in CMOS Process

Abstract

This paper presents the design and experimental results of a digital acquisition system based on a chopper-stabilized Instrumentation Amplifier with Common-Mode feedback for CMRR enhancement. Chopping techniques are used to remove both offset and flicker noise, detrimental effects characteristic of pure CMOS processes. A second-order, discrete-time, single-bit Sigma-Delta ADC with CIFB structure is used to convert the signal into the digital domain where it can be processed in real time to diagnose and report urgencies. Measurements on a 0.6μm process have shown that the input CMRR is boosted by 71dB when the feedback is closed through the patient. The input referred integrated noise for the overall system within the ECG band frequencies of 0.1Hz to 400Hz (including the quantization noise) is 4.2μVP, below the recommended maximum detection error of 10.0μVP.