2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)最新文献_第7页

On UVM Reliability in Mixed-Signal Verification 混合信号验证中的UVM可靠性研究

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667543

Wilmer Ramirez, H. Gómez, E. Roa

引用次数: 8

A Pseudo-Raised Cosine IR-UWB pulse generator with adaptive PSD using 130nm CMOS process 基于130纳米CMOS工艺的伪升余弦红外超宽带脉冲发生器

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667582

L. C. Moreira, J. F. Neto, Walter Silva Oliveira, Thiago Ferauche, Guilherme Apolinario Silva Novaes

{"title":"A Pseudo-Raised Cosine IR-UWB pulse generator with adaptive PSD using 130nm CMOS process","authors":"L. C. Moreira, J. F. Neto, Walter Silva Oliveira, Thiago Ferauche, Guilherme Apolinario Silva Novaes","doi":"10.1109/LASCAS.2019.8667582","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667582","url":null,"abstract":"This paper presents the design of a Pseudo-Raised Cosine Impulse Radio Ultra-Wide Band (IR-UWB) pulse generator with adaptive PSD (Power Spectrum Density) that produces pulse shaping just altering the number of oscillations and amplitude. The complete pulse generator circuit is composed of 11 blocks of edge combiner stages implemented with high impedance circuits each, a digital control block, and a filter. This circuit can generate from four to eleven oscillations per clock edge to compose a PRC (Pseudo-Raised Cosine) at the output. The proposed circuit operates at about 10.3 GHz and generates three basic pulses, with a range of 10, 20 and 30 mV and four other amplitude combinations. The post-layout simulations were performed using the Cadence Spectrum/Virtuoso, and the dynamic energy varied from 5.02 fJ with four oscillations to 16.11 fJ with eleven oscillations per pulse, respectively. Thus, the maximum PSD peak is −60 dBm, the minimum is −72 dBm with a voltage supply of 1.2 V. Finally, the Pulse Repetition Frequency (PRF) of 100 MHz and the size of the main chip occupies an area of 0.042 mm2 (without pads).","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130480873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Low-Power and High-Throughput Approximate 4×4 DCT Hardware Architecture 低功耗和高吞吐量近似4×4 DCT硬件架构

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667581

Mateus Leme, L. Braatz, D. Palomino, L. Agostini, M. Porto

引用次数: 1

On-Chip Solar Energy Harvesting System Using Substrate Diode PV Cell and Fractional Open Circuit Voltage MPPT Implementation 基于衬底二极管PV电池和分数开路电压MPPT的片上太阳能收集系统的实现

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667566

D. Rodriguez, Carlos Bernal, G. Serrano

引用次数: 5

A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller 基于RISC-V的低功耗微控制器的低面积直接存储器访问控制器体系结构

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667579

Hanssel Morales, Ckristian Duran, E. Roa

引用次数: 5