On UVM Reliability in Mixed-Signal Verification

Abstract

During the last decade, Universal Verification Methodology (UVM) has become a popular standard test methodology for verification of intellectual property (VIP) within digital and mixed-signal systems. UVM prominent features include stimulus automation, I/O checking and code reuse. This paper analyzes the strengths and weaknesses of UVM along with measurements of reliability using a 32-bit LPDDR3 memory interface and a bandgap voltage reference. Simulation results indicate that reliability is limited by complexity of the circuit under test and proper UVM setup to get considerable analog simulation coverage. For analog cases, UVM-AMS can render low reliability considering that a common practice in analog design is creating multiple testbenches according to the function/domain tested. VIP by itself should be used as a complement to traditional verification practices even when assuming access to a fully detailed UVM-AMS VIP.