2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)最新文献_第6页

An All-Thin-Devices Level Shifter in Standard-Cell Format for Auto Place-and-Route Flow 用于自动放置和路由流的标准单元格式的全薄器件电平移位器

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667578

Nestor Cuevas, Javier Ardila, E. Roa

引用次数: 2

Dedicated monitoring service without routing mitigation for Networks-on-Chip 针对片上网络的专用监视服务，不带路由缓解

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667560

Gabriel Ganzer, M. Berejuck

引用次数: 0

Evaluation of Distortion Level in Analog Multipliers through DC Analysis Only 仅通过直流分析评估模拟乘法器的失真水平

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667570

Gabriele Costa Goncalves, Mario Henrique Oliva Pereira Silva, F. Andrade, F. Cardoso, Antonio José Sobrinho de Sousa, E. Santana, A. Cunha

引用次数: 1

ASC-FFT: Area-Efficient Low-Latency FFT Design Based on Asynchronous Stochastic Computing ASC-FFT:基于异步随机计算的区域高效低延迟FFT设计

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667599

Patricia Gonzalez-Guerrero, Xinfei Guo, M. Stan

{"title":"ASC-FFT: Area-Efficient Low-Latency FFT Design Based on Asynchronous Stochastic Computing","authors":"Patricia Gonzalez-Guerrero, Xinfei Guo, M. Stan","doi":"10.1109/LASCAS.2019.8667599","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667599","url":null,"abstract":"Asynchronous Stochastic Computing (ASC) is a new paradigm that addresses Synchronous Stochastic Computing (SSC) drawbacks, expensive stochastic number generation (SNG) and long latency, by using continuous time streams (CTS). To go beyond the basic operations of addition and multiplication in ASC we need to incorporate a memory element. Although for SSC the natural memory element is a clocked-flip-flop, using the same approach with no synchronized data leads to unacceptable large error. In this paper, we propose to use a capacitor embedded in a feedback loop as the ASC memory element. Based on this idea, we design a low-error asynchronous adder that stores the carry information in the capacitor. Our adder enables the implementation of more complex computation logic. As an example, we implement an asynchronous stochastic Fast Fourier Transform (ASC-FFT) using a FinFET1X1 technology. The proposed adder requires 76%-24% less hardware cost compared against conventional and SSC adders respectively. Besides, the ASC-FFT shows 3X less latency when compared with SSC-FFT approaches and significant improvements in latency and area over conventional FFT architectures with no degradation of the computation accuracy measured by the FFT Signal to Noise Ratio (SNR).","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114542101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Facilitating Fault-Simulation Comprehension through a Fault-Lists Analysis Tool 通过故障列表分析工具促进故障模拟理解

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667573

P. Bernardi, D. Piumatti, E. Sánchez

{"title":"Facilitating Fault-Simulation Comprehension through a Fault-Lists Analysis Tool","authors":"P. Bernardi, D. Piumatti, E. Sánchez","doi":"10.1109/LASCAS.2019.8667573","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667573","url":null,"abstract":"The complexity of modern embedded processors used in safety-critical applications requires in-field self-test strategies. The most popular ones are based on hardware and software-based approaches such as Logic-BIST (L-BIST) and Software-Based Self-Test (SBST). While the first one requires to include in the device additional hardware, the second consists on the execution of a set of assembly programs, usually called a Software Test Library (STL). In this context, in case the STL strategy is adopted for infield testing of the device, a very time consuming task is necessary to validate the final results of the test library. This process includes fault simulation for every test program and aims at determine the actual contribution that a given test may provide to the final test library, by manipulating intermediate results, comparing, including, and excluding the test program results with respect to all the others. This task is useful, for example, to understand whether the changes made to a test program produced a gain in the final fault coverage or not. In this paper, we propose for the very first time, a Fault List Analysis Tool that is able to support the development of a STL by performing some fault-list oriented operations on the preliminary results obtained during the development process. Some experimental results were gathered during the STL development for various industrial processors.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123681109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Delta-Sigma modulated output temperature sensor for 1V voltage supply δ - σ调制输出温度传感器为1V电压供应

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667536

J. Ramírez, Joao P. Tiol, Diego Deotti, F. Fruett

引用次数: 2

A Simplified Tool for Testing of Feature Selection and Classification Algorithms in Motor Imagery of Right and Left Hands of EEG Signals 一种简化的脑电信号左右运动图像特征选择与分类算法测试工具

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667568

Giovanna Bonafe Bernardi, T. Pimenta, R. Moreno

{"title":"A Simplified Tool for Testing of Feature Selection and Classification Algorithms in Motor Imagery of Right and Left Hands of EEG Signals","authors":"Giovanna Bonafe Bernardi, T. Pimenta, R. Moreno","doi":"10.1109/LASCAS.2019.8667568","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667568","url":null,"abstract":"Some algorithms or a combination of them are more appropriated than others depending on the type of data that is being analyzed and what features and parameters are being used. In the analysis of motor imagery (MI) in an offline EEG-based brain-computer interface (BCI), different codes with different parameters are often used, making it harder to compare the effects of the algorithms applied. In this paper, we propose a simplified and limited tool that aims to aid in the testing of feature extraction, selection and classification algorithms separately or combined for the analysis of motor imagery in offline EEG-based brain signals while providing some information about the intermediate steps of a BCI construction. A known data set is used in order to ease the comparison between other researches. Only data from channels C3, Cz and C4 are used and the MI of left hand and right hand are analyzed. The data is filtered using a band-pass Chebyshev type II filter between 5 and 35Hz. Then, The rhythms mu and beta are isolated using a discrete wavelet transform (DWT) algorithm with a db4 mother wavelet of level 5. The proposed system has two outputs: the coefficients of the DWT related to the rhythms mu and beta; and a feature vector with three chosen features that can be used as an input to a classifier. The features extracted are mean, variance and energy. These are simple but effective features. Fixing some of the parameters simplifies the tool, offers a better environment for comparison of algorithms and allows the user to focus on specific steps of a BCI construction such as the feature selection and the classification phases.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"53 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116477412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Recognition of emotions using ICEEMD-based characterization of multimodal physiological signals 基于iceemd的多模态生理信号表征的情绪识别

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667585

O. A. Ordóñez-Bolaños, J. Gómez-Lara, M. A. Becerra, Diego Hernán Peluffo-Ordóñez, C. Duque-Mejía, D. Medrano-David, Cristian Mejía-Arboleda

{"title":"Recognition of emotions using ICEEMD-based characterization of multimodal physiological signals","authors":"O. A. Ordóñez-Bolaños, J. Gómez-Lara, M. A. Becerra, Diego Hernán Peluffo-Ordóñez, C. Duque-Mejía, D. Medrano-David, Cristian Mejía-Arboleda","doi":"10.1109/LASCAS.2019.8667585","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667585","url":null,"abstract":"Physiological-signal-analysis-based approaches are typically used for automatic emotion identification. Given the complex nature of signals-related emotions, their right identification often results in a non-trivial and exhaustive process -especially because such signals suffer from high dependence upon multiple external variables. Some emotional criteria of interest are arousal, valence, and dominance. Several research works have addressed this issue, mainly through creating prediction systems, notwithstanding, due to aspects such as accuracy, in-context interpretation and computational cost, it is still considered a great-of-interest, open research eld. This paper is aimed at verifying the usefulness of the so-called improved complete empirical mode decomposition (ICEEMD) as a physiological-signal-characterization building block within an emotion-predicting system. To this purpose, some physiological signals along with patients’ metadata from the DEAP database are considered. The experiments are set-up as follows: Signals are pre-processed by amplitude adjusting and simple filtering. Then, a feature set is built using HC, and multiple statistic measures from information given by the three considered decompositions, namely: ICEEMD, discrete wavelet transform (DWT),and Maximal overlap DWT. Subsequently, Relief F selection algorithm was applied for reducing the dimensionality of the feature space. Finally, classifiers (LDC and K-NN cascade architectures) are used to assess the class-separability given by the feature set. The different decomposition techniques were compared, and the relevant signals and measures were established. Experimental results evidence the suitability of ICEEMD decomposition for physiological-signal-driven emotions analysis.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115086218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Programmable and Low-Area On-Die Termination for High-Speed Interfaces 一种用于高速接口的可编程低面积片内终端

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667552

Luisa Dovale, Juan Sebastian Moya, E. Roa

引用次数: 1

Resilient Hardware Design for Critical Systems 关键系统的弹性硬件设计

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667549

M. Farias, N. Nedjah, P. V. Carvalho

{"title":"Resilient Hardware Design for Critical Systems","authors":"M. Farias, N. Nedjah, P. V. Carvalho","doi":"10.1109/LASCAS.2019.8667549","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667549","url":null,"abstract":"With the constant breakthroughs in technology components, there has been an increase in the capacity and performance of FPGA. Nevertheless, new methods to keep fault tolerance at an appropriate level for critical applications in hardware must be considered, particularly due to the transient nature of some radiation-induced faults. The most commonly used methods to mitigate these faults involve redundancy, such as the Triple Modular Redundancy (TMR) with the 2 out of 3 voter solution (2oo3), the most common passive method, in addition to active methods, such as the replacement of resources allocated a priori or dynamic recovery. The objective of this study is to propose a hardware architecture that increases the reliability in the use of circuits implemented in FPGAs, in addition to the one found in circuits with TMR, but without significant increase the area required by the redundant solution. The proposed solution uses comparators, a state machine-based controller and a multiplexer module to operate an architecture with three redundant modules and a spare one. The analysis shows that the proposed architecture is more reliable and keeps this reliability for longer periods of time than redundant solutions that use more area, such as the 3 out of 5 configuration (3oo5).","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129106536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3