A Programmable and Low-Area On-Die Termination for High-Speed Interfaces

Abstract

Although much progress has been made over the years in high-speed I/O, there is no comprehensive characterization of their termination design. In contrast to the widespread notion that a programmable termination might not offer any challenge, electromigration in conjunction with ESD compliance and programmability demand considerable attention during the termination design. Here we combine a design methodology and circuit techniques to address the hinted challenges. Overall, our study provides a comprehensive characterization on the design of a 35Ω-to-65Ω matching network. As a result, this paper presents a programmable ESD-compliant on-die termination occupying an area of 0.03mm2 on a standard 180nm CMOS with a maximum worst case of 7.14mA static current consumption.