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2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)最新文献

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Post-Silicon Debugging Platform with Bus Monitoring Capability to Perform Behavioral and Performance Analyses 后硅调试平台与总线监控能力，以执行行为和性能分析
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667537
Wilmer Ramirez, E. Roa
{"title":"Post-Silicon Debugging Platform with Bus Monitoring Capability to Perform Behavioral and Performance Analyses","authors":"Wilmer Ramirez, E. Roa","doi":"10.1109/LASCAS.2019.8667537","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667537","url":null,"abstract":"Post-silicon debugging systems must offer run-control capability and visibility on complex SoC in order to detect/analyze errors and find possible design enhancements. This paper presents a scalable and reusable debugging platform for post-silicon validation. The platform is composed of a debug module with JTAG communication and a bus monitor. Relevant features are core control, system bus operation, and non-intrusive monitoring. A flexible filtering allows selecting transfers of interest or performing a general monitoring of the SoC. Captured data can be analyzed by performance counters that check executed and finished transfers, calculating their latency to detect deadlocks in the system. The debugging platform has been implemented as part of a SoC with a 32-bit RISC-V based core and multiple peripherals.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127374509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Sub-µW Reconfigurable Front-End for Invasive Neural Recording 一种用于侵入性神经记录的亚µW可重构前端
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667584
José Luis Valtierra, R. Fiorelli, M. Delgado-Restituto, Á. Rodríguez-Vázquez
{"title":"A Sub-µW Reconfigurable Front-End for Invasive Neural Recording","authors":"José Luis Valtierra, R. Fiorelli, M. Delgado-Restituto, Á. Rodríguez-Vázquez","doi":"10.1109/LASCAS.2019.8667584","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667584","url":null,"abstract":"This paper presents a sub-µW ac-coupled reconfigurable front-end for the purpose of neural recording. The proposed topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180 nm CMOS process draws a maximum of 815 nW from a 1 V source. The measured input-referred spot-noise at 500 Hz is ${text{75}},{text{nV}}/sqrt {{text{Hz}}} $ while the integrated noise in the 200 Hz - 5 kHz band is 4.1 µVrms.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128310023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
4D Bidirectional Lattice Digital Filters 4D双向点阵数字滤波器
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667598
M. Kousoulis, C. A. Coutras, G. Antoniou
{"title":"4D Bidirectional Lattice Digital Filters","authors":"M. Kousoulis, C. A. Coutras, G. Antoniou","doi":"10.1109/LASCAS.2019.8667598","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667598","url":null,"abstract":"A four–dimension (4D) bidirectional digital filter, having a minimum number of delay elements, is presented. This filter, besides having a minimum number of delay elements, also has an absolutely minimal state–space vector. Furthermore the transfer function, of the proposed 4D filter, is characterized by the all–pass property as in the well known classical one–dimension (1D) case. Four–dimension and two–dimension (2D) low–order examples are provided to show the features of the circuit and state–space realization structures.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"37 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114134309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An asymmetrical bulk-modified composite MOS transistor with enhanced linearity 一种具有增强线性度的非对称体改性复合MOS晶体管
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667576
A. Arnaud, Rafael Puyol, A. Chacón-Rodríguez, M. Miguez, J. Gak
{"title":"An asymmetrical bulk-modified composite MOS transistor with enhanced linearity","authors":"A. Arnaud, Rafael Puyol, A. Chacón-Rodríguez, M. Miguez, J. Gak","doi":"10.1109/LASCAS.2019.8667576","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667576","url":null,"abstract":"In this work, an asymmetrical bulk-linearized composite MOSFET is presented, with an enhanced linear range and an equivalent saturation voltage of up to several hundred mV even in weak inversion, allowing to implement large MOS resistors. Some preliminary measurements are presented, as well as 150MΩ and 200MΩ equivalent resistors simulations, with a linear range up to 1.5V. A low frequency, 40dB gain, fully integrated cardiac sensing channel filter/amplifier is also shown. Taking advantage of the proposed technique, the circuit consumes only 25nA of supply current.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126930562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A State Assignment Method for Extended Burst-Mode gC Finite State Machines Based on Genetic Algorithm 基于遗传算法的扩展突发模式gC有限状态机状态分配方法
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667601
T. Curtinhas, D. L. Oliveira, G. Batista, Vitor L. V. Torres, L. Romano
{"title":"A State Assignment Method for Extended Burst-Mode gC Finite State Machines Based on Genetic Algorithm","authors":"T. Curtinhas, D. L. Oliveira, G. Batista, Vitor L. V. Torres, L. Romano","doi":"10.1109/LASCAS.2019.8667601","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667601","url":null,"abstract":"This paper proposes a new algorithm for state assignment of Extended Burst-Mode Asynchronous Finite State Machines (XBM_AFSM). The proposal is based on genetic algorithm and it introduces a novel style of state assignment. It improves the results and it overcomes the previous methods found in literature once it addresses the \"state minimization\", the \"critical race free coding\" and \"coverage\" as a single problem. Furthermore, it is able to detect the conflicts in XBM specification and to insert the minimum number of state variables in the XBM specification in order to eliminate those conflicts. A dedicated computational tool called SAGAAs_gC implemented the algorithm and it was tested in a set of 39 XBM benchmarks. When it is compared to 3D tool, our method achieved an average reduction of 21.4%, 16.5% and 12.12% in amount of state variables, number of literals and transistors, respectively. Results show that the method and dedicated computational tool SAGAAs_gC achieved good and reliable results, showing a high potential of practical implementation in actual circuit designs.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129695183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ISFETs: theory, modeling and chip for characterization isfet:理论，建模和芯片表征
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667572
Rodrigo Wrege, M. C. Schneider, J. G. Guimarães, C. Galup-Montoro
{"title":"ISFETs: theory, modeling and chip for characterization","authors":"Rodrigo Wrege, M. C. Schneider, J. G. Guimarães, C. Galup-Montoro","doi":"10.1109/LASCAS.2019.8667572","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667572","url":null,"abstract":"The ISFET (Ion Sensitive Field Effect Transistor) is a structure based on the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is capable of measuring ionic concentration of a solution. The ISFET has been used for such areas as DNA sequencing, viruses and bacteria detection. The basic idea behind the ISFETs emerged in 1970, but a deeper understanding of some of its non-idealities and the development of architectures to reduce their effects are still needed. For that reason, this work revisits the basic principles of ISFET operation. The ISFET modeling using the binding site theory, Gouy-Chapman-Stern model and the Advanced Compact Model of the transistor is introduced and implemented in Matlab®. Furthermore, the details of a chip designed on the Virtuoso® platform, aimed at characterizing the ISFETs on the SilTerra D18V technology, are presented. Simulation results estimate an average sensitivity of 45.3 mV/pH for the designed devices over a pH range from 1 to 10. The chip sent for fabrication was kindly supported by Chipus Microeletrônica S.A. and SilTerra Malaysia Sdn Bhd.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122238585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Signal Reconstruction Technique For Power Delivery Analysis 一种用于电力输送分析的信号重构技术
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667556
Carlos J. Franco-Tinoco, Ricardo Astro-Bohorquez, Daniel Garcia-Mora
{"title":"A Signal Reconstruction Technique For Power Delivery Analysis","authors":"Carlos J. Franco-Tinoco, Ricardo Astro-Bohorquez, Daniel Garcia-Mora","doi":"10.1109/LASCAS.2019.8667556","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667556","url":null,"abstract":"This document describes a signal processing technique to reconstruct the high-frequency current of a DDR4 DIMM at BGA level, by using the current measured at a remote shunt resistor.Simulation results using the reconstructed current show very good correlation with experimental data, proving that the proposed approach is an accurate, reliable low-cost low-complexity characterization technique.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129540508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.8V 9bit 10MS/s SAR ADC in 0.18µm CMOS for bioimpedance analysis 1.8V 9bit 10MS/s SAR ADC, 0.18µm CMOS，用于生物阻抗分析
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667565
Daniele Santana, H. Hernández, W. Noije
{"title":"A 1.8V 9bit 10MS/s SAR ADC in 0.18µm CMOS for bioimpedance analysis","authors":"Daniele Santana, H. Hernández, W. Noije","doi":"10.1109/LASCAS.2019.8667565","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667565","url":null,"abstract":"In this work a 9-bits low power 10MS/s asynchronous SAR ADC in 180nm CMOS tecnology is presented. The ADC core occupies an active area of 0.124mm2. The ADC main parameters were extracted from post-layout simulations, which resulted in SNR of 55.29dB and ENOB of 8.59 bit at 1.8Vsupply and a sampling frequency of 10MS/s while consuming 0.692mW. The Figure of Merit (FoM) obtained was 145.93 fJ/conversion-step","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog-to-Information Converter Based on Off-the-Shelf Components and SoC-FPGA 基于现成元件和SoC-FPGA的模拟-信息转换器
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667546
A. López-Parrado, Alexander Vera-Tasama, Juan Felipe Medina Lee, Duvier de Jesus Bohorquez-Palacio
{"title":"Analog-to-Information Converter Based on Off-the-Shelf Components and SoC-FPGA","authors":"A. López-Parrado, Alexander Vera-Tasama, Juan Felipe Medina Lee, Duvier de Jesus Bohorquez-Palacio","doi":"10.1109/LASCAS.2019.8667546","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667546","url":null,"abstract":"This paper presents design and implementation of a 100-MHz Analog-to-Information Converter (AIC) based on Random Demodulator (RD); for this purpose, we used off-the-shelf components to implement the analog front-end and a SoC-FPGA chip to implement the digital hardware/software subsystem. Analog front-end is composed of one mixer and one low-pass filter, which were implemented by using a Gilbert Cell and a passive RC circuit, respectively. Hardware/software sub-system was implemented on the Field Programmable Array (FPGA) and Hard Processor System (HPS) sides of the SoC-FPGA chip, where FPGA side was used to implement the hardware that manages RD and HPS side was used to implement spectrum recovery algorithms. Finally, verification results showed that designed AIC can recover sparse signals of 100 MHz bandwidth, where a sub-Nyquist rate of 4 MHz is used along with two Compressive Sensing (CS) recovery algorithms.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122379938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of Foundation Fieldbus H1 Controller IC 基金会现场总线H1控制器IC的研制
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667588
T. P. Mussolini, F. Ramos, R. Moreno, T. Pimenta
{"title":"Development of Foundation Fieldbus H1 Controller IC","authors":"T. P. Mussolini, F. Ramos, R. Moreno, T. Pimenta","doi":"10.1109/LASCAS.2019.8667588","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667588","url":null,"abstract":"This work presents the implementation of a Foundation Fieldbus Controller circuit to provide interface to CPU/MCU. The implemented integrated circuit satisfies the high performance requirements of industrial network equipments, according to IEC 61158-2. The circuit consists of Manchester encoder/decoder, time-critical hardware timers and other functions necessary to implement the data link layer for industrial networks using Foundation Fieldbus H1 protocols. The communication between the CPU/MPU and the proposed device is conducted by I2C serial communication standard. This paper describes the main characteristics of the developed ASIC. The circuit was fabricated on XFAB XH035 CMOS technology and it can be used as an alternative to commercial models that work with the old parallel ports that are leaving the market.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115252312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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