Post-Silicon Debugging Platform with Bus Monitoring Capability to Perform Behavioral and Performance Analyses

Abstract

Post-silicon debugging systems must offer run-control capability and visibility on complex SoC in order to detect/analyze errors and find possible design enhancements. This paper presents a scalable and reusable debugging platform for post-silicon validation. The platform is composed of a debug module with JTAG communication and a bus monitor. Relevant features are core control, system bus operation, and non-intrusive monitoring. A flexible filtering allows selecting transfers of interest or performing a general monitoring of the SoC. Captured data can be analyzed by performance counters that check executed and finished transfers, calculating their latency to detect deadlocks in the system. The debugging platform has been implemented as part of a SoC with a 32-bit RISC-V based core and multiple peripherals.