2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)最新文献_第4页

Analytical Modeling of Chaotic Sampling of Regular Waveform for Random Number Generation 随机数生成规则波形混沌采样的解析建模

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667545

Kaya Demir, Salih Ergun

引用次数: 4

Memristor device fabricated from doped graphene oxide 由掺杂氧化石墨烯制成的忆阻器器件

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667547

M. Sparvoli, M. Gazziro, Jonas S. Marma, Gabriel Zucchi

{"title":"Memristor device fabricated from doped graphene oxide","authors":"M. Sparvoli, M. Gazziro, Jonas S. Marma, Gabriel Zucchi","doi":"10.1109/LASCAS.2019.8667547","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667547","url":null,"abstract":"Resistive switching (RS) is the basic phenomenon for the operation of resistive memory ReRAM. A specific electrical voltage is applied in the MIM (metal-insulator-metal) device, it can undergo switching from its initial insulator resistance state (HRS - high resistance state) to a low resistance state (LRS). There is a strong relationship between the materials used in the composition of these devices and their characteristics. In this work, resistive memory based on silver-doped graphene oxide was characterized and its voltage response varying as a function of voltage was obtained. SET and RESET are caused by the redox reactions of graphene oxide layer at the interface between electrodes. Defects as oxygen vacancies in oxide material play a key role for the resistive switching. There is another factor that can influence the operation of this device and threshold switching: silver present in the graphene oxide composition could interfere with the filament formation. In summary, the resistive switching behavior of rGO+0.1%Ag/GO+1%Ag/Al device was investigated, which reveals electric characteristics and SET/RESET voltages. In addition, a threshold switching characteristic is revealed.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132046122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Digital Random Number Generator Based on Irregular Sampling of Regular Waveform 基于规则波形不规则采样的数字随机数发生器

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667580

Burak Acar, Salih Ergun

{"title":"A Digital Random Number Generator Based on Irregular Sampling of Regular Waveform","authors":"Burak Acar, Salih Ergun","doi":"10.1109/LASCAS.2019.8667580","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667580","url":null,"abstract":"There is an increasing demand for the security of information over the past few decades. Random Number Generators (RNGs) play a significant role in many cryptographic applications for generating unpredictable bit-streams. Despite the fact that Application Specific Integrated Circuit (ASIC) implementation of RNGs are usually preferred for their high performance, fully digital circuits implemented on Field Programmable Gate Array (FPGA) platforms are more attractive for designers considering their ability of rapid-reconfigurable prototyping, and their easy integration to other digital circuits. In this study, a new improvement based on irregular sampling of regular waveform is proposed for ring oscillator based RNGs. It is subjected to National Institute of Standards and Technology (NIST) 800-22 test suite and it passes full tests without any post-processing. An attack circuit is also implemented to see the robustness of the designed RNG against coupling-based attacks. No effective correlation can be obtained between the outputs of the target and the attack circuit; in spite of, their extremely close placement to each other inside the FPGA chip. The feasibility of the proposed method is given in experimental results.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133002434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations 异步准随机数生成器:利用PVT变化

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667561

Rodrigo N. Wuerdig, M. Sartori, Ney Laert Vilar Calazans

引用次数: 1

Behavioral Modeling of Pre-emphasis Drivers Including Power Supply Noise Using Neural Networks 基于神经网络的包括电源噪声的预强调驱动行为建模

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667589

Huan Yu, J. Shin, T. Michalka, M. Larbi, M. Swaminathan

引用次数: 2

Optimized Fault-Tolerant Buffer Design for Network-on-Chip Applications 片上网络应用的优化容错缓冲器设计

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667550

A. Pinheiro, J. Silveira, D. A. B. Tavares, Felipe Silva, C. Marcon

{"title":"Optimized Fault-Tolerant Buffer Design for Network-on-Chip Applications","authors":"A. Pinheiro, J. Silveira, D. A. B. Tavares, Felipe Silva, C. Marcon","doi":"10.1109/LASCAS.2019.8667550","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667550","url":null,"abstract":"Newest technologies of integrated circuits manufacture allow billions of transistors arranged in a single chip, which requires a communication architecture with high scalability and parallelism degree, such as a Network-on-Chip (NoC). As the technology scales down, the probability of Multiple Cell Upsets (MCUs) increases, being Error Correction Code (ECC) the most used technique to protect stored information against MCUs. NoC buffers are components that suffer from MCUs induced by diverse sources, such as radiation and electromagnetic interference. Thereby, applying ECCs in NoC buffers may come as a solution for reliability issues, although increasing the design cost and requiring a buffer with higher storage capacity. This paper proposes an optimized buffer using an Extended Hamming code to deal with MCUs and enhance the protected information storage, pursuing to reduce the area and power required for ECC implementation. We guide the optimized buffer evaluation by measuring the fault tolerance efficiency, buffer area, power overhead and performance of the proposed technique. All tests included the comparison with a non-optimal appliance of ECC in a NoC buffer. The results show the proposed technique reduces the area and power overhead in buffers with ECC and allows a considerable fault tolerance against MCUs with a small performance impact.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124539914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS 65纳米CMOS低噪声容错辐射强化2.56 Gbps高速前馈校正时钟数据恢复电路

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667542

J. Prinzie, S. Kulis, P. Leitao, R. Francisco, V. D. Smedt, P. Moreira, P. Leroux

引用次数: 12

Clip Clustering for Early Lithographic Hotspot Classification 早期光刻热点分类的Clip聚类方法

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667548

A. Oliveira, Julia Casarin Puget, C. Metzler, R. Reis

{"title":"Clip Clustering for Early Lithographic Hotspot Classification","authors":"A. Oliveira, Julia Casarin Puget, C. Metzler, R. Reis","doi":"10.1109/LASCAS.2019.8667548","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667548","url":null,"abstract":"Early lithography hotspot detection is critical to improving manufacturing yield. EDA tools have been proposed to detect potentially problematic patterns during physical design and physical verification stages. Considering that detailed lithography simulation has a high computational cost for full-chip scale, the pattern matching method proved to be a fast solution with good accuracy due to a set of pre-characterized patterns as input. It is proposed a clip clustering method for pattern classification in early detection of lithography hotspots. We focus at both clip representation and clip clustering stage that is the major challenge of this method. It was performed experiments on 2016 ICCAD contest benchmark suite, and results show the efficiency of our clustering approach. The algorithm supports both area and edge constrained clustering. Our solution generates on average 9.4% fewer clusters than the contest winner while staying within 16% range on average from the state of the art algorithms. Moreover, Our clustering pattern-driven layout strategy outperforms the 2016 ICCAD winner on runtime by up to 60%.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122871301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliability Assessment in Transmission Considering Intermittent Energy Resources 考虑间歇性能源的输电系统可靠性评估

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667564

Alfredo G. Tobon, H. Chamorro, F. Gonzalez-Longatt, V. Sood

引用次数: 12

[Front matter] (前页)

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/lascas.2019.8667558

引用次数: 0