65纳米CMOS低噪声容错辐射强化2.56 Gbps高速前馈校正时钟数据恢复电路

J. Prinzie, S. Kulis, P. Leitao, R. Francisco, V. D. Smedt, P. Moreira, P. Leroux
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引用次数: 12

摘要

提出了一种用于高能物理和空间应用的容错、抗辐射时钟和数据恢复(CDR)体系结构。CDR采用了一种新型的软容错压控振荡器(VCO),并包括一个高速前馈路径来稳定CDR,以补偿VCO中额外的极,使其免受电离粒子的影响。CDR具有2.56 Gbps的数据速率,并使用in - phase /Quadrature (IQ)时钟与频率检测器(FD)相结合来增加拉入范围。该电路采用65纳米CMOS技术设计,核心功耗仅为34兆瓦。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path to stabilize the CDR to compensate for an additional pole in the VCO to harden it against ionizing particles. The CDR has a data rate of 2.56 Gbps and uses In-Phase/Quadrature (IQ) clocks in combination with a frequency detector (FD) to increase the pull-in range. The circuit was designed in a 65 nm CMOS technology and has a core power consumption of only 34 mW.
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