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2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)最新文献

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A 130 nm CMOS LNA for Satellite Application 卫星应用的130nm CMOS LNA
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667595
R. Timbo, H. Klimach, E. Fabris
{"title":"A 130 nm CMOS LNA for Satellite Application","authors":"R. Timbo, H. Klimach, E. Fabris","doi":"10.1109/LASCAS.2019.8667595","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667595","url":null,"abstract":"This work presents the design of a narrowband Low Noise Amplifier (LNA) that is a part of a transponder project of a UHF satellite for the Brazilian Environmental Data Collecting System (SBCDA). The proposed LNA operates at 401.635 MHz moreover, it provides 28dB of power gain, 3.6dB of noise figure (NF), IIP3 of -28 dBm and 6.53 mW of power consumption and it was designed in a standard 130 nm CMOS process.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115000807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Accelerating Template Matching for Efficient Object Tracking 加速模板匹配的有效目标跟踪
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667596
A. V. Cardoso, N. Nedjah, L. M. Mourelle
{"title":"Accelerating Template Matching for Efficient Object Tracking","authors":"A. V. Cardoso, N. Nedjah, L. M. Mourelle","doi":"10.1109/LASCAS.2019.8667596","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667596","url":null,"abstract":"Template matching is used to determine the degree of similarity between two images of the same size. Pearson’s Correlation Coefficient is applied, due to its property of invariance to brightness changes. This coefficient is computed for each image pixel, entailing a computationally intensive task. In order to accelerate this process, a dedicated co-processor was designed to implement this computation. To improve the search for the maximum correlation point between the image and the template, we used, in this work, Bacteria Foraging Optimization, one of the swarm intelligence strategies. The search process is run by an embedded general purpose processor. The work presented in this paper describes the implementation of the embedded system and compares the results obtained here to those previously obtained when using other swarm intelligent strategies.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126456210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders 具有LOA不精确加法器的低功耗近似SAD结构
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667554
R. Porto, L. Agostini, B. Zatt, N. Roma, M. Porto
{"title":"Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders","authors":"R. Porto, L. Agostini, B. Zatt, N. Roma, M. Porto","doi":"10.1109/LASCAS.2019.8667554","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667554","url":null,"abstract":"Approximate computing is a highly promising approach to reduce the computational effort in video encoders. Its use is even more relevant and advantageous when high resolution videos must be processed in real time using battery powered devices. In this scenario, it is essential to reduce power dissipation and silicon area. In particular, the distortion metric calculation module is one of the most time demanding and the Sum of Absolute Differences (SAD) is usually the most used distortion metric, mainly when dedicated hardware is considered. To overcome this demand, this paper presents a power-efficient SAD architecture compliant with current video encoders based on the usage of Lower-Part-OR Adders (LOA). The attained results showed that important power (17.99%) and area (30.56%) savings can be reached, with an increase of only 0.3% in BD-rate. When compared with state of the art related works, the designed architecture reaches the best area and power dissipation results.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129743029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Voltage CMOS Quaternary Gates for Digital Designs 用于数字设计的电压CMOS四元门
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667539
Milton E. R. Romero, E. M. Martins, D. C. A. Arigoni, A. D. M. Nogueira, M. E. D. Gonzalez
{"title":"Voltage CMOS Quaternary Gates for Digital Designs","authors":"Milton E. R. Romero, E. M. Martins, D. C. A. Arigoni, A. D. M. Nogueira, M. E. D. Gonzalez","doi":"10.1109/LASCAS.2019.8667539","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667539","url":null,"abstract":"To take advantage of the Multiple Valued Logic, with domain: {0, 1,…, N – 1}, where N is the a base of representation, set of integrated circuits (IC) that implement the MVL operators is needed. In the IC implementation, it is necessary to minimize the number of transistors to improve area utilization and power consumption, among other advantages. This work proposes an implementation of gates: eAND3, eAND2, eAND1, Successor, and MAX, with only 14, 28, 6, 26, and 3 MOS transistors, using Austriamicrosystems 0.35µm technology; such that, the number of transistors utilized in the proposed implementation is lower than the number of transistors for equivalent gates reported in literature. The inverted threshold voltage measured have changed 30% in different process variation corners (models cmostm, cmoswp, cmosws) nevertheless, the simulations demonstrate correct behavior for all gates.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":" 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120830973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures 一种电容负载平面谐振结构的分割算法
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667583
I. Erdin, R. Achar
{"title":"A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures","authors":"I. Erdin, R. Achar","doi":"10.1109/LASCAS.2019.8667583","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667583","url":null,"abstract":"The segmentation method used for the analysis of arbitrarily shaped planar structures is extended to a more general form to account for capacitive loading between parallel plates. In power integrity (PI) analysis of power delivery networks (PDN), the capacitive loading represents decoupling capacitors between power and ground planes. The algorithm is geared to the analysis of PDNs for performance evaluation, selection and placement of decoupling capacitors. For linear circuits, the proposed integrated algorithm eliminates the commonly used two-step approach. In the case of nonlinear loads, the algorithm helps to reduce the size of modified admittance matrix (MNA) and relaxes the burden of following circuit simulation. The proposed method is validated in comparison to a numerical electromagnetic (EM) simulator.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"49 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
About Performance Faults in Microprocessor Core in-field Testing 微处理器内核现场测试中的性能故障
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667562
J. P. Acle, E. Sánchez, M. Reorda
{"title":"About Performance Faults in Microprocessor Core in-field Testing","authors":"J. P. Acle, E. Sánchez, M. Reorda","doi":"10.1109/LASCAS.2019.8667562","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667562","url":null,"abstract":"When microprocessor-based devices are used in safety-critical applications (e.g., in automotive systems), it is common to adopt solutions aimed at testing them in-field, so that permanent faults that may affect them are identified before they cause critical consequences. In this way, the required reliability figures can be achieved. A popular solution to perform in-field test (especially when executed concurrently to the application) is based on triggering the execution of proper procedures (composing a Self-Test Library, or STL), which are able to activate faults and make them visible when checking the produced results (e.g., in memory). Unfortunately, a special class of faults exists (named Performance Faults), which do not impact the value of the results, but only the timing behavior of the processor. This paper describes a set of experiments aimed at quantitatively evaluating the number of these faults in a simple processor core, and outlines some observation techniques that can be used for their detection.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"43 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131893969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior 在CMOS锁存器中引入非对称性以获得固有的上电复位行为
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667593
F. L. Cabrera, Fernando Sousa, H. Pettenghi
{"title":"Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior","authors":"F. L. Cabrera, Fernando Sousa, H. Pettenghi","doi":"10.1109/LASCAS.2019.8667593","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667593","url":null,"abstract":"A very important characteristic of sequential circuits is the initial state of the registers. Commonly, it is not possible to guarantee the logic value of the registers after the energizing of the circuit, so their initial values are forced through a Power-On-Reset module. In this paper we propose an asymmetric alternative to the conventional CMOS latch topology, which ensures its initial stored value without the use of additional circuits. We present the theoretical considerations that determine the initial state in the conventional and new topologies. Since the geometry of the transistors used to create the asymmetry is equal to that of the conventional circuit, the same occupied area is kept. A flip-flop was fabricated in CMOS 130 nm using both topologies. The measurements over 16 different samples demonstrated the correct functionality of the new topology when compared to the conventional one.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134334678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Tools Flow for Synthesis of Asynchronous Control Circuits from Extended STG Specifications 从扩展STG规范合成异步控制电路的工具流程
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667591
Higor A. Delsoto, D. L. Oliveira, G. Batista, Diego A. Silva, L. Romano
{"title":"A Tools Flow for Synthesis of Asynchronous Control Circuits from Extended STG Specifications","authors":"Higor A. Delsoto, D. L. Oliveira, G. Batista, Diego A. Silva, L. Romano","doi":"10.1109/LASCAS.2019.8667591","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667591","url":null,"abstract":"Asynchronous control circuits are very important in heterogeneous systems, existing two different specifications previously proposed to describe the asynchronous controls: the Signal Transition Graph (STG) and the Extended Burst Mode (XBM). These specifications, despite being quite popular, present certain limitations in describing some interfaces for heterogeneous systems. In this paper, we propose a tools flow for the automatic synthesis of asynchronous control circuits that are described by the specification called Extended Signal Transition Graph (XSTG). XSTG has all features of STG and XBM specifications. For a set of benchmarks, the XSTG description shows high compaction in addition to a natural ability to describe conditional signals, in the case an average reduction of 54.3% in places and 47.4% in transitions, when it is compared with STG specification.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128731712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FPGA IP for Real-time 4K HDR Image Decoding in VR Devices VR设备中实时4K HDR图像解码的FPGA IP
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667541
Kamlakannan Kamalavasan, Ratnasegar Natheesan, K. Pradeep, Sivakumaran Gowthaman, S. Aravinth, A. Pasqual
{"title":"FPGA IP for Real-time 4K HDR Image Decoding in VR Devices","authors":"Kamlakannan Kamalavasan, Ratnasegar Natheesan, K. Pradeep, Sivakumaran Gowthaman, S. Aravinth, A. Pasqual","doi":"10.1109/LASCAS.2019.8667541","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667541","url":null,"abstract":"Quad High Definition (QHD/4K) Virtual Reality (VR) Headsets with High Dynamic Range (HDR) technology will provide a superior experience to users. Wireless VR headsets are attractive as it offers freedom on mobility and higher user comfort. Cloud and workstations are capable of rendering 4K HDR scenes in real-time with ease. The efficient transmission of these scenes through wireless network requires the use of compression techniques. Decoding 4K HDR frames at VR devices in real-time is a challenge. Given the power and memory efficiency of the hardware decoders, in this paper we propose JPEG-XT Profile C based hardware architecture to decode 4K HDR frames in real-time. We employ novel methods for merged base and residual layer decoding pipelines, design of probability-based hybrid Huffman lookup table architecture and sparsity aware inverse zig-zag processing. Our decoder is implemented in Xilinx VC707 board and achieved the decoding performance of 4K HDR frames at 30fps while consuming only 7K of LUTs, 12K of Registers and 1980Kb of block memory. Single clocked architecture, use of clock enabling logic and resource sharing in time reduced power consumption to less than 1 watt.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125664735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Output Voltage Regulation For dc–dc Buck Converters: a Passivity–Based PI Design dc-dc降压变换器的输出电压调节:一种基于无源的PI设计
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) Pub Date : 2019-02-01 DOI: 10.1109/LASCAS.2019.8667557
W. Gil-González, O. Montoya, A. Garcés, F. Serra, Guillermo Magaldi
{"title":"Output Voltage Regulation For dc–dc Buck Converters: a Passivity–Based PI Design","authors":"W. Gil-González, O. Montoya, A. Garcés, F. Serra, Guillermo Magaldi","doi":"10.1109/LASCAS.2019.8667557","DOIUrl":"https://doi.org/10.1109/LASCAS.2019.8667557","url":null,"abstract":"This paper presents a global tracking passivity–based proportional–integral (PI) control for output voltage regulation of a dc–dc Buck converter. The proposed controller is based on passivity formulation since dc–dc Buck converter has a passive structure in open–loop. Additionally, the controller takes advantage of the PI actions to design a control law that guarantees asymptotically stability in the Lyapunov’s sense under closed–loop operation. The proposed controller does not depend on the parameters, which makes it a robust controller. The robustness of the proposed controller is checked by comparing its dynamical performance in front of a conventional PID controller. All simulation results were fulfilled via MATLAB software.","PeriodicalId":142430,"journal":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131979016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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