Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior

Abstract

A very important characteristic of sequential circuits is the initial state of the registers. Commonly, it is not possible to guarantee the logic value of the registers after the energizing of the circuit, so their initial values are forced through a Power-On-Reset module. In this paper we propose an asymmetric alternative to the conventional CMOS latch topology, which ensures its initial stored value without the use of additional circuits. We present the theoretical considerations that determine the initial state in the conventional and new topologies. Since the geometry of the transistors used to create the asymmetry is equal to that of the conventional circuit, the same occupied area is kept. A flip-flop was fabricated in CMOS 130 nm using both topologies. The measurements over 16 different samples demonstrated the correct functionality of the new topology when compared to the conventional one.