Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders

Approximate computing is a highly promising approach to reduce the computational effort in video encoders. Its use is even more relevant and advantageous when high resolution videos must be processed in real time using battery powered devices. In this scenario, it is essential to reduce power dissipation and silicon area. In particular, the distortion metric calculation module is one of the most time demanding and the Sum of Absolute Differences (SAD) is usually the most used distortion metric, mainly when dedicated hardware is considered. To overcome this demand, this paper presents a power-efficient SAD architecture compliant with current video encoders based on the usage of Lower-Part-OR Adders (LOA). The attained results showed that important power (17.99%) and area (30.56%) savings can be reached, with an increase of only 0.3% in BD-rate. When compared with state of the art related works, the designed architecture reaches the best area and power dissipation results.