Voltage CMOS Quaternary Gates for Digital Designs

Abstract

To take advantage of the Multiple Valued Logic, with domain: {0, 1,…, N – 1}, where N is the a base of representation, set of integrated circuits (IC) that implement the MVL operators is needed. In the IC implementation, it is necessary to minimize the number of transistors to improve area utilization and power consumption, among other advantages. This work proposes an implementation of gates: eAND3, eAND2, eAND1, Successor, and MAX, with only 14, 28, 6, 26, and 3 MOS transistors, using Austriamicrosystems 0.35µm technology; such that, the number of transistors utilized in the proposed implementation is lower than the number of transistors for equivalent gates reported in literature. The inverted threshold voltage measured have changed 30% in different process variation corners (models cmostm, cmoswp, cmosws) nevertheless, the simulations demonstrate correct behavior for all gates.