Resilient Hardware Design for Critical Systems

With the constant breakthroughs in technology components, there has been an increase in the capacity and performance of FPGA. Nevertheless, new methods to keep fault tolerance at an appropriate level for critical applications in hardware must be considered, particularly due to the transient nature of some radiation-induced faults. The most commonly used methods to mitigate these faults involve redundancy, such as the Triple Modular Redundancy (TMR) with the 2 out of 3 voter solution (2oo3), the most common passive method, in addition to active methods, such as the replacement of resources allocated a priori or dynamic recovery. The objective of this study is to propose a hardware architecture that increases the reliability in the use of circuits implemented in FPGAs, in addition to the one found in circuits with TMR, but without significant increase the area required by the redundant solution. The proposed solution uses comparators, a state machine-based controller and a multiplexer module to operate an architecture with three redundant modules and a spare one. The analysis shows that the proposed architecture is more reliable and keeps this reliability for longer periods of time than redundant solutions that use more area, such as the 3 out of 5 configuration (3oo5).