Low-Power and High-Throughput Approximate 4×4 DCT Hardware Architecture

Abstract

Mobile devices with multimedia processing capabilities are becoming more and more present, despite their energy restrictions. On the other hand, multimedia applications are very demanding tasks, which have a negative impact on the battery lifetime of mobile phones. Nonetheless, video encoding, one of the most demanding multimedia applications, can benefit from approximate computing to save energy. This paper proposes an approximate 4×4 Discrete Cosine Transform (DCT) hardware architecture using the imprecise Lower Part-OR Adder (LOA). The imprecise operators, such as LOA, are one of many approaches to approximate computing. This approximate hardware architecture is developed with different imprecision levels. The presented approximate 4×4 DCT hardware architecture synthesis results show area reduction up to 13.6%, power savings up to 23% and throughput increase up to 26.45% while having a negligible to small BD-Rate impact.