Antonio José Sobrinho de Sousa, F. Cardoso, Kelvin Kefren Carvalho Feitosa Nunes, F. Andrade, Gabriele Costa Goncalves, E. Santana, A. Cunha
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A Very Compact CMOS Analog Multiplier for Application in CNN Synapses
This work presents a CMOS analog multiplier architecture for application as the synapse in analog cellular neural networks. The circuit comprises two voltage-mode inputs and a current-mode output. Simulated performance features obtained from a circuit design in CMOS 130 nm technology include: +100 mV input voltage range, 23 µW static power, −32 dB maximum total harmonic distortion and −3 dB bandwidth of 51.2 kHz. The active area totalizes only 40 µm2.
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