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International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)最新文献

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Antimony assisted arsenic S/D extension (A/sup 3/ SDE) engineering for sub-0.1 /spl mu/m nMOSFETs : a novel approach to steep and retrograde indium pocket profiles 用于低于0.1 /spl mu/m的nmosfet的锑辅助砷S/D扩展(A/sup 3/ SDE)工程:一种陡峭和逆行铟口袋轮廓的新方法
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979403
H. Wang, C.C. Wang, C. Hsieh, S. Lu, M. Chiang, Y. Chu, C. Chen, T. Ong, Tahui Wang, P. Griffin, C. H. Diaz
{"title":"Antimony assisted arsenic S/D extension (A/sup 3/ SDE) engineering for sub-0.1 /spl mu/m nMOSFETs : a novel approach to steep and retrograde indium pocket profiles","authors":"H. Wang, C.C. Wang, C. Hsieh, S. Lu, M. Chiang, Y. Chu, C. Chen, T. Ong, Tahui Wang, P. Griffin, C. H. Diaz","doi":"10.1109/IEDM.2001.979403","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979403","url":null,"abstract":"We propose a novel process whereby Antimony Assisted Arsenic Source/Drain Extension (A/sup 3/ SDE) is employed to realize a steep and retrograde indium pocket profile for sub-0.1 /spl mu/m nMOSFETs. By engineering the defect distributions in the amorphous layer created by an indium implant, this new process improves by 8% the current drive while maintaining the same I/sub off/. It reduces nMOS diode leakage by two orders of magnitude and sidewall junction capacitance near the gate by 14%. Reliability assessment of devices fabricated by the A/sup 3/ SDE process reveals significant improvement in hot carrier effects and no observable degradation of gate oxide integrity.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"3.4.1-3.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86768961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 130 nm generation high density Etox/sup TM/ flash memory technology 采用130纳米一代高密度Etox/sup TM/闪存技术
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979398
S. Keeney
{"title":"A 130 nm generation high density Etox/sup TM/ flash memory technology","authors":"S. Keeney","doi":"10.1109/IEDM.2001.979398","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979398","url":null,"abstract":"A 130 nm-generation flash memory technology has been developed, optimized for small cell size, high performance low voltage operation and multi-level-cell and embedded logic capability. Memory cell scaling utilizes the architecture features from the 180 nm technology along with channel erase, advanced 130 nm lithography, dielectric scaling, junction scaling, dual trench and dual spacer technology. 32 Mbit flash memories with a 0.16 um/sup 2/ cell size have been built on this technology showing good yield, performance and reliability.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"14 1","pages":"2.5.1-2.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91145936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications OUM -用于独立和嵌入式应用的180nm非易失性存储单元元件技术
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979636
S. Lai, T. Lowrey
{"title":"OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications","authors":"S. Lai, T. Lowrey","doi":"10.1109/IEDM.2001.979636","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979636","url":null,"abstract":"This paper discusses the development status of the memory cell element of OUM (Ovonic Unified Memory) - a chalcogenide-based, phase-change nonvolatile semiconductor memory technology at the 180 nm technology node. The device structure and characterization of the memory element will be reviewed. The key characteristics of the technology will be discussed for ultra-high density, low voltage, high-speed programming, high cycle count, high read speed, and competitive cost structure nonvolatile memory for stand alone and embedded applications. This technology is inherently radiation resistant and is bit byte or word programmable without the requirement of Flash-like block erase. Low voltage and energy operation make OUM an attractive candidate for mobile applications.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"68 1","pages":"36.5.1-36.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89320033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 309
A 185 GHz f/sub max/ SOI DTMOS with a new metallic overlay-gate for low-power RF applications 185ghz f/sub max/ SOI DTMOS，采用新型金属覆盖栅极，适用于低功率射频应用
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979672
T. Hirose, Y. Momiyama, M. Kosugi, H. Kano, Y. Watanabe, T. Sugii
{"title":"A 185 GHz f/sub max/ SOI DTMOS with a new metallic overlay-gate for low-power RF applications","authors":"T. Hirose, Y. Momiyama, M. Kosugi, H. Kano, Y. Watanabe, T. Sugii","doi":"10.1109/IEDM.2001.979672","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979672","url":null,"abstract":"The dynamic threshold MOS transistor (DTMOS) built on an SOI substrate is one candidate to realize low-power one-chip RF and high-speed digital integrated circuits for wireless communication systems and optical fiber links. Scaling down the characteristic length of the DTMOS is aggressively performed, and the cut-off frequency (f/sub T/) has been drastically increased. Although the f/sub T/ is steeply rising every year, improvement of the maximum oscillation frequency (f/sub max/) is very slow. This is due to a limitation of the silicide based gate resistance (Rg) in the conventional logic CMOS process. Many interesting ways with optimized layout such as folded gate finger and multi-finger pattern have been proposed, and great efforts to make Rg small have been made. The most effective way to perform further reduction of Rg is to use a low resistive metal-gate or a metallic overlay-gate that is fabricated on the poly-Si fine gate. In this paper, we propose an 80 nm gate SOI-nDTMOS with a new gate structure. The key is to introduce a metallic overlay-gate process into the conventional logic CMOS fabrication process. Using the metallic overlay-gate structure, we achieved the f/sub max/ of 185 GHz at low bias voltage, which is, in our knowledge, the world record ever reported for Si MOSFETs.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"33.5.1-33.5.3"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90228833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A very high efficiency silicon bipolar transistor 一种非常高效的硅双极晶体管
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979654
F. Carrara, A. Scuderi, G. Tontodonato, G. Palmisano
{"title":"A very high efficiency silicon bipolar transistor","authors":"F. Carrara, A. Scuderi, G. Tontodonato, G. Palmisano","doi":"10.1109/IEDM.2001.979654","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979654","url":null,"abstract":"The potential of a high-performance low-cost silicon bipolar technology for high-efficiency low-voltage RF power amplifiers was explored. To this end, a unit power cell was developed by optimizing layout design, collector thickness and doping level. On-wafer load-pull measurements were performed which showed an excellent power-added efficiency of 83% at 1.8 GHz under a supply voltage of 2.7 V. Additionally, a 1-W output power and a 74% PAE were achieved by a multi-cell packaged device with on-board testing.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"55 1","pages":"40.1.1-40.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77401089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Weibull slopes, critical defect density, and the validity of stress-induced-leakage current (SILC) measurements 威布尔斜率，临界缺陷密度，以及应力诱发泄漏电流(SILC)测量的有效性
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979448
E. Wu, J. Suñé, E. Nowak, W. Lai, J. McKenna
{"title":"Weibull slopes, critical defect density, and the validity of stress-induced-leakage current (SILC) measurements","authors":"E. Wu, J. Suñé, E. Nowak, W. Lai, J. McKenna","doi":"10.1109/IEDM.2001.979448","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979448","url":null,"abstract":"Voltage, temperature, and polarity dependence of Weibull slopes are carefully measured using area scaling method over a wide range of voltages and temperatures for several oxide thickness (T/sub OX/) values in comparison with direct method. We investigate the validity of stress-induced-leakage-current (SILC), /spl Delta/J/J/sub 0|BD/, as a measure for the critical defect density, N/sub BD/. Our finding clearly shows that the /spl Delta/J/J/sub 0|BD/ cannot be used as a reliable measure of N/sub BD/. This work suggests that a re-evaluation of the breakdown models constructed from the SILC-based measurements is required in gate oxide reliability community, in particular, their validity in comparison with the statistically accurate breakdown data.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"82 1","pages":"6.3.1-6.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83251057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Interconnecting device opportunities for gigascale integration (GSI) 千兆级集成(GSI)的互连设备机会
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979560
J. Meindl, R. Venkatesan, J.A. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Bakir, T. Mule, P. Kohl, K. Martin
{"title":"Interconnecting device opportunities for gigascale integration (GSI)","authors":"J. Meindl, R. Venkatesan, J.A. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Bakir, T. Mule, P. Kohl, K. Martin","doi":"10.1109/IEDM.2001.979560","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979560","url":null,"abstract":"In recent years interconnecting devices have become primary limits on the performance, energy dissipation, signal integrity, and productivity of gigascale integration (GSI). Opportunities to address the interconnect problem include new materials and processes, reverse scaling, novel microarchitectures, three-dimensional integration, input/output interconnect enhancements, RF wireless interconnects and microphotonics.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"23 1","pages":"23.1.1-23.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83532733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Highly reliable 1 Mbit ferroelectric memories with newly developed BLT thin films and steady integration schemes 采用新开发的BLT薄膜和稳定集成方案的高可靠的1mbit铁电存储器
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979633
B. Yang, Y. Kang, S. Lee, K. Noh, N. Kim, S. Yeom, N. Kang, H. G. Yoon
{"title":"Highly reliable 1 Mbit ferroelectric memories with newly developed BLT thin films and steady integration schemes","authors":"B. Yang, Y. Kang, S. Lee, K. Noh, N. Kim, S. Yeom, N. Kang, H. G. Yoon","doi":"10.1109/IEDM.2001.979633","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979633","url":null,"abstract":"Highly reliable packaged 1 Mbit ferroelectric memories with 0.35 /spl mu/m CMOS ensuring ten-year retention and imprint at 175/spl deg/C have been successfully developed for the first time. These excellent reliabilities have resulted from newly developed BLT ferroelectric films with superior performance and steady integration schemes free from attacks of process impurities.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"98 1","pages":"36.2.1-36.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83577979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
1.6 w/mm, 26% PAE AlGaN/GaN HEMT operation at 29GHz 1.6 w/mm, 26% PAE AlGaN/GaN HEMT工作在29GHz
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979670
R. Sandhu, M. Wojtowicz, M. Barsky, R. Tsai, I. Smorchkova, C. Namba, P. Liu, R. Dia, M. Truong, D. Ko, J. Yang, H. Wang, M.A. Khan
{"title":"1.6 w/mm, 26% PAE AlGaN/GaN HEMT operation at 29GHz","authors":"R. Sandhu, M. Wojtowicz, M. Barsky, R. Tsai, I. Smorchkova, C. Namba, P. Liu, R. Dia, M. Truong, D. Ko, J. Yang, H. Wang, M.A. Khan","doi":"10.1109/IEDM.2001.979670","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979670","url":null,"abstract":"In this paper, we report the first GaN HEMT power device to operate at 29 GHz. The 0.2 μm T-gate AlGaN/GaN HEMT with a 120 μm total gate periphery exhibited a pulsed output power of 1.6 W/mm with a gain of 6.7 dB and an associated power aided efficiency of 26% at 29 GHz. The epitaxial layers were grown by MOCVD on SiC.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"26 1","pages":"17.5.1-17.5.3"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89410971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
CMP-free and CMP-less approaches for multilevel Cu/low-k BEOL integration 多层Cu/低k BEOL集成的无cmp和无cmp方法
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979408
M. Tsai, S.W. Chou, C. Chang, C.H. Hsieha, M.W. Lin, C.M. Wu, W. Shue, D. Yu, M. Liang
{"title":"CMP-free and CMP-less approaches for multilevel Cu/low-k BEOL integration","authors":"M. Tsai, S.W. Chou, C. Chang, C.H. Hsieha, M.W. Lin, C.M. Wu, W. Shue, D. Yu, M. Liang","doi":"10.1109/IEDM.2001.979408","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979408","url":null,"abstract":"A CMP-free process by electropolishing (EP) the planar contact plating (CP) Cu film and TaN dry etching which eliminate the stress induced peeling during CMP was demonstrated. Nanometer smoothness and a highly <111> texture of Cu can be achieved by optimizing the EP process. A 4-level Cu/low-k interconnect with CMP-less process was demonstrated with excellent yield. This process improves the throughput on ECP and CMP by two and has less dishing.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"4.3.1-4.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87461195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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