H. Wang, C.C. Wang, C. Hsieh, S. Lu, M. Chiang, Y. Chu, C. Chen, T. Ong, Tahui Wang, P. Griffin, C. H. Diaz
{"title":"用于低于0.1 /spl mu/m的nmosfet的锑辅助砷S/D扩展(A/sup 3/ SDE)工程:一种陡峭和逆行铟口袋轮廓的新方法","authors":"H. Wang, C.C. Wang, C. Hsieh, S. Lu, M. Chiang, Y. Chu, C. Chen, T. Ong, Tahui Wang, P. Griffin, C. H. Diaz","doi":"10.1109/IEDM.2001.979403","DOIUrl":null,"url":null,"abstract":"We propose a novel process whereby Antimony Assisted Arsenic Source/Drain Extension (A/sup 3/ SDE) is employed to realize a steep and retrograde indium pocket profile for sub-0.1 /spl mu/m nMOSFETs. By engineering the defect distributions in the amorphous layer created by an indium implant, this new process improves by 8% the current drive while maintaining the same I/sub off/. It reduces nMOS diode leakage by two orders of magnitude and sidewall junction capacitance near the gate by 14%. Reliability assessment of devices fabricated by the A/sup 3/ SDE process reveals significant improvement in hot carrier effects and no observable degradation of gate oxide integrity.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"3.4.1-3.4.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Antimony assisted arsenic S/D extension (A/sup 3/ SDE) engineering for sub-0.1 /spl mu/m nMOSFETs : a novel approach to steep and retrograde indium pocket profiles\",\"authors\":\"H. Wang, C.C. Wang, C. Hsieh, S. Lu, M. Chiang, Y. Chu, C. Chen, T. Ong, Tahui Wang, P. Griffin, C. H. Diaz\",\"doi\":\"10.1109/IEDM.2001.979403\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a novel process whereby Antimony Assisted Arsenic Source/Drain Extension (A/sup 3/ SDE) is employed to realize a steep and retrograde indium pocket profile for sub-0.1 /spl mu/m nMOSFETs. By engineering the defect distributions in the amorphous layer created by an indium implant, this new process improves by 8% the current drive while maintaining the same I/sub off/. It reduces nMOS diode leakage by two orders of magnitude and sidewall junction capacitance near the gate by 14%. Reliability assessment of devices fabricated by the A/sup 3/ SDE process reveals significant improvement in hot carrier effects and no observable degradation of gate oxide integrity.\",\"PeriodicalId\":13825,\"journal\":{\"name\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"volume\":\"1 1\",\"pages\":\"3.4.1-3.4.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2001.979403\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979403","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Antimony assisted arsenic S/D extension (A/sup 3/ SDE) engineering for sub-0.1 /spl mu/m nMOSFETs : a novel approach to steep and retrograde indium pocket profiles
We propose a novel process whereby Antimony Assisted Arsenic Source/Drain Extension (A/sup 3/ SDE) is employed to realize a steep and retrograde indium pocket profile for sub-0.1 /spl mu/m nMOSFETs. By engineering the defect distributions in the amorphous layer created by an indium implant, this new process improves by 8% the current drive while maintaining the same I/sub off/. It reduces nMOS diode leakage by two orders of magnitude and sidewall junction capacitance near the gate by 14%. Reliability assessment of devices fabricated by the A/sup 3/ SDE process reveals significant improvement in hot carrier effects and no observable degradation of gate oxide integrity.