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International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)最新文献

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Record Q spiral inductors in standard CMOS 在标准CMOS中记录Q螺旋电感
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979674
L. Tiemeijer, D. Leenaerts, N. Pavlovic, R. Havens
{"title":"Record Q spiral inductors in standard CMOS","authors":"L. Tiemeijer, D. Leenaerts, N. Pavlovic, R. Havens","doi":"10.1109/IEDM.2001.979674","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979674","url":null,"abstract":"High-Q spiral inductors, either realized as discrete elements in thin-film technologies, or as integrated components in IC processes, are essential to realize key RF circuitry like VCO's and LNA's. We have demonstrated for the first time that by dividing a spiral inductor into four parallel current paths of equal resistance and inductance current crowding can be suppressed, allowing a record Q of 15 for a 2 GHz 5 nH inductor in standard CMOS, representing a 40 % improvement over previous art. The proposed division into parallel current paths can be realized without process modifications, reduces CMP dishing, and is expected to provide even larger performance gains in terms of quality factor Q and inductor area for IC and thin-film processes employing thicker metal layers and low-K materials.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"41 1","pages":"40.7.1-40.7.3"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88107538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
MOSFET design of 100 nm node low standby power CMOS technology compatible with embedded trench DRAM and analog devices MOSFET设计的100 nm节点低待机功耗CMOS技术兼容嵌入式沟槽DRAM和模拟器件
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979556
A. Oishi, R. Hasumi, Y. Okayama, K. Miyashita, M. Oowada, S. Aota, T. Nakayama, M. Matsumoto, N. Inada, T. Hiraoka, H. Yoshimura, Y. Asahi, Y. Takegawa, T. Yoshida, K. Sunouchi, A. Yasumoto, Y. Tateshita, M. Ueshima, T. Morikawa, T. Umebayashi, T. Gocho, F. Matsuoka, T. Noguchi, M. Kakumu
{"title":"MOSFET design of 100 nm node low standby power CMOS technology compatible with embedded trench DRAM and analog devices","authors":"A. Oishi, R. Hasumi, Y. Okayama, K. Miyashita, M. Oowada, S. Aota, T. Nakayama, M. Matsumoto, N. Inada, T. Hiraoka, H. Yoshimura, Y. Asahi, Y. Takegawa, T. Yoshida, K. Sunouchi, A. Yasumoto, Y. Tateshita, M. Ueshima, T. Morikawa, T. Umebayashi, T. Gocho, F. Matsuoka, T. Noguchi, M. Kakumu","doi":"10.1109/IEDM.2001.979556","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979556","url":null,"abstract":"Demonstrates an optimum design of low leakage 85nm gate CMOSFET (I/sub off//spl les/3pA//spl mu/m) for 100nm technology node. Gate dielectric module has been optimized to achieve low gate leakage, low flicker noise and sufficiently high driving current. Deep source/drain design is strongly restricted from controlling junction leakage current when integration of trench DRAM cell is considered. Especially, for nMOSFET, deep junction is formed only by using phosphorus to suppress defect creation. Short channel immunity and suppression of gate depletion are achieved simultaneously by introducing gate pre-doping technique. In addition, channel and halo profiles are optimized to reduce band-to-band tunneling (BTBT) current. As a result, we have achieved excellent performance of /spl Sigma/CV/I(=CV/I/sub dn/+CV/I/sub dp/)=10.8psec with I/sub off/=3pA//spl mu/m at V/sub dd/ of 1.2V.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"34 1","pages":"22.4.1-22.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86561237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Organic thin film phototransistors and fast circuits 有机薄膜光电晶体管和快速电路
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979621
D. Gundlach, L. Zhou, J. A. Nichols, J. Huang, C. Sheraw, T. Jackson
{"title":"Organic thin film phototransistors and fast circuits","authors":"D. Gundlach, L. Zhou, J. A. Nichols, J. Huang, C. Sheraw, T. Jackson","doi":"10.1109/IEDM.2001.979621","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979621","url":null,"abstract":"We have fabricated organic thin film transistors (OTFTs) using the small-molecule organic semiconductor naphthacene as the active layer material with field-effect mobility greater than 0.1 cm/sup 2//V-s. This mobility is acceptable for several large-area electronic applications. OTFTs fabricated using naphthacene films show a large photosensitivity, of potential interest for applications requiring phototransistors. The threshold voltage and subthreshold region electrical characteristics of naphthacene OTFTs allow the fabrication of OTFT circuits without active layer patterning and do not require the use of a level shift stage such as that used to fabricate pentacene OTFT circuits. 5-stage ring oscillators fabricated with naphthacene OTFTs have single-stage propagation delay of less than 28 /spl mu/s; the fastest organic circuits reported to date.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"22 1","pages":"34.1.1-34.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79695749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A micromachined integratable thermal reactor 一种微机械集成热反应堆
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979514
Q. Zou, U. Sridhar, Yu Chen, J. Singh, E. Seluanayagam, T. Lim, Tie Yan, I. Rodriguez, M. Lesaicherre
{"title":"A micromachined integratable thermal reactor","authors":"Q. Zou, U. Sridhar, Yu Chen, J. Singh, E. Seluanayagam, T. Lim, Tie Yan, I. Rodriguez, M. Lesaicherre","doi":"10.1109/IEDM.2001.979514","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979514","url":null,"abstract":"This paper presents a micromachined thermal reactor. The silicon substrate remains unheated because of the thermal isolation design during thermal cycling of the reaction chamber. The side-heating concept employed has significantly improved in-chamber temperature uniformity. Finite-element-analysis is carried out to optimise the thermal performance. Experimental results have proved that the thermal reactor can easily be integrated with other non-thermal components. Integration of the device with other components or modules of miniaturised total analysis systems (/spl mu/TAS) is very promising.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"25 1","pages":"16.5.1-16.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81195777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A general partition scheme for gate leakage current suitable for MOSFET compact models 一种适用于MOSFET紧凑型栅漏电流的通用划分方案
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979487
W. Shih, R. Rios, P. Packan, K. Mistry, T. Abbott
{"title":"A general partition scheme for gate leakage current suitable for MOSFET compact models","authors":"W. Shih, R. Rios, P. Packan, K. Mistry, T. Abbott","doi":"10.1109/IEDM.2001.979487","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979487","url":null,"abstract":"For the first time, it is rigorously shown that the source/drain partition of gate leakage current in a MOSFET is identical to that of inversion charge. This paper provides model developers a general recipe in addressing the partition issue and enables more consistent model parameter extraction methodology for MOSFETs in sub-100 nm technology.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"58 2 1","pages":"13.3.1-13.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79836691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Ultrathin high-K gate stacks for advanced CMOS devices 用于先进CMOS器件的超薄高k栅极堆叠
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979537
E. Gusev, D. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. Jamison, D. Neumayer, M. Copel, M. Gribelyuk, H. Okorn-Schmidt, C. D'Emic, P. Kozłowski, K. Chan, N. Bojarczuk, L. Ragnarsson, P. Ronsheim, K. Rim, R. Fleming, A. Mocuta, A. Ajmera
{"title":"Ultrathin high-K gate stacks for advanced CMOS devices","authors":"E. Gusev, D. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. Jamison, D. Neumayer, M. Copel, M. Gribelyuk, H. Okorn-Schmidt, C. D'Emic, P. Kozłowski, K. Chan, N. Bojarczuk, L. Ragnarsson, P. Ronsheim, K. Rim, R. Fleming, A. Mocuta, A. Ajmera","doi":"10.1109/IEDM.2001.979537","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979537","url":null,"abstract":"Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"22 1","pages":"20.1.1-20.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74037050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 215
3D analytical subthreshold and quantum mechanical analyses of double-gate MOSFET 双栅MOSFET的三维解析亚阈值和量子力学分析
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979432
G. Pei, V. Narayanan, Zengtao Liu, E. Kan
{"title":"3D analytical subthreshold and quantum mechanical analyses of double-gate MOSFET","authors":"G. Pei, V. Narayanan, Zengtao Liu, E. Kan","doi":"10.1109/IEDM.2001.979432","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979432","url":null,"abstract":"Scaling studies on double-gate MOSFET and its variations are critical to CMOS technology node below 70 nm. In this work we present 3D analytical modeling in the subthreshold region and analytical quantum mechanical considerations of channel coupling that can facilitate device design and technology selection. The analytical models are corroborated with both experiments and distributed simulation.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"44 1","pages":"5.3.1-5.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73687435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Electrical degradation of InAlAs/InGaAs metamorphic high-electron mobility transistors InAlAs/InGaAs变质高电子迁移率晶体管的电降解
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979464
S. Mertens, J. D. del Alamo
{"title":"Electrical degradation of InAlAs/InGaAs metamorphic high-electron mobility transistors","authors":"S. Mertens, J. D. del Alamo","doi":"10.1109/IEDM.2001.979464","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979464","url":null,"abstract":"We have studied the electrical degradation of InAlAs/InGaAs Metamorphic HEMTs. The main effect of the application of a bias for an extended period of time is a severe increase in the drain resistance, R/sub D/, of the device. We have identified two different degradation modes: a reduction in the sheet-electron concentration of the extrinsic drain and an increase of the drain contact resistance. Both mechanisms are found to be directly related to impact-ionization. The metamorphic nature of the substrate does not seem to play a role in the observed degradation.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"9.2.1-9.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74167313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement 局部机械应力控制(LMC)是一种提高cmos性能的新技术
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979529
A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, F. Ootsuka
{"title":"Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement","authors":"A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, F. Ootsuka","doi":"10.1109/IEDM.2001.979529","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979529","url":null,"abstract":"We have developed a new technique, called \"local mechanical-stress control\" (LMC), to enhance CMOS current drivability. It utilizes high mechanical stress produced by a SiN layer and Ge-ion implantation to selectively relax the stress of the layer. The drive currents of both n- and p-MOSFETs can be improved by controlling the stress of the SiN layer selectively. The effects of LMC become more significant as devices become smaller, and the drive current is estimated to increase by more than 20% in future 70-nm CMOS technology.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"41 1","pages":"19.4.1-19.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86833760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 87
Wide bandgap semiconductor devices and MMICs for RF power applications 用于射频功率应用的宽带隙半导体器件和mmic
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979517
J. Palmour, S. Sheppard, R.P. Smith, S. Allen, W. Pribble, T.J. Smith, Z. Ring, J. Sumakeris, A. Saxler, J. Milligan
{"title":"Wide bandgap semiconductor devices and MMICs for RF power applications","authors":"J. Palmour, S. Sheppard, R.P. Smith, S. Allen, W. Pribble, T.J. Smith, Z. Ring, J. Sumakeris, A. Saxler, J. Milligan","doi":"10.1109/IEDM.2001.979517","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979517","url":null,"abstract":"High power densities of 5.2 W/mm and 63% power added efficiency (PAE) have been demonstrated for SiC MESFETs at 3.5 GHz. Wide bandwidth MMICs have also been demonstrated with SiC MESFETs, yielding 37 W at 3.5 GHz. Even higher power densities have been obtained with GaN HEMTs, showing up to 12 W/mm under pulsed conditions. Hybrid amplifiers using GaN HEMTs on SiC substrates have demonstrated a pulsed output power level of 50.1 W, with 8 dB gain and PAE of 28% at 10 GHz, and CW power levels of 36 W have also been obtained. A wide bandwidth GaN MMIC amplifier had a peak pulsed power level of 24.2 watts, with a gain of 12.8 dB and PAE of 22% at 16 GHz.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"46 1","pages":"17.4.1-17.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85864806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
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