A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, F. Ootsuka
{"title":"Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement","authors":"A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, F. Ootsuka","doi":"10.1109/IEDM.2001.979529","DOIUrl":null,"url":null,"abstract":"We have developed a new technique, called \"local mechanical-stress control\" (LMC), to enhance CMOS current drivability. It utilizes high mechanical stress produced by a SiN layer and Ge-ion implantation to selectively relax the stress of the layer. The drive currents of both n- and p-MOSFETs can be improved by controlling the stress of the SiN layer selectively. The effects of LMC become more significant as devices become smaller, and the drive current is estimated to increase by more than 20% in future 70-nm CMOS technology.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"41 1","pages":"19.4.1-19.4.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"87","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979529","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 87
Abstract
We have developed a new technique, called "local mechanical-stress control" (LMC), to enhance CMOS current drivability. It utilizes high mechanical stress produced by a SiN layer and Ge-ion implantation to selectively relax the stress of the layer. The drive currents of both n- and p-MOSFETs can be improved by controlling the stress of the SiN layer selectively. The effects of LMC become more significant as devices become smaller, and the drive current is estimated to increase by more than 20% in future 70-nm CMOS technology.