用于先进CMOS器件的超薄高k栅极堆叠

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI:10.1109/IEDM.2001.979537

E. Gusev, D. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. Jamison, D. Neumayer, M. Copel, M. Gribelyuk, H. Okorn-Schmidt, C. D'Emic, P. Kozłowski, K. Chan, N. Bojarczuk, L. Ragnarsson, P. Ronsheim, K. Rim, R. Fleming, A. Mocuta, A. Ajmera

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引用次数: 215

摘要

回顾了高k高温(/spl sim/1000/spl℃)多晶硅CMOS工艺和器件的最新进展并概述了问题，并展示了可能的解决方案。具体来说，我们讨论了器件特性，如栅极漏电流，平带电压位移，电荷捕获，通道迁移率，以及集成和处理方面。通过不同的沉积技术在硅上沉积各种高钾候选材料，包括HfO/sub 2/、Al/sub 2/O/sub 3/、HfO/sub 2//Al/sub 2/O/sub 3/、ZrO/sub 2/、硅酸盐和AlN/sub y/(O/sub x/)，说明了高k介电集成到当前Si技术中的复杂问题。

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Ultrathin high-K gate stacks for advanced CMOS devices

Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.

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International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)

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