{"title":"采用130纳米一代高密度Etox/sup TM/闪存技术","authors":"S. Keeney","doi":"10.1109/IEDM.2001.979398","DOIUrl":null,"url":null,"abstract":"A 130 nm-generation flash memory technology has been developed, optimized for small cell size, high performance low voltage operation and multi-level-cell and embedded logic capability. Memory cell scaling utilizes the architecture features from the 180 nm technology along with channel erase, advanced 130 nm lithography, dielectric scaling, junction scaling, dual trench and dual spacer technology. 32 Mbit flash memories with a 0.16 um/sup 2/ cell size have been built on this technology showing good yield, performance and reliability.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"14 1","pages":"2.5.1-2.5.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"A 130 nm generation high density Etox/sup TM/ flash memory technology\",\"authors\":\"S. Keeney\",\"doi\":\"10.1109/IEDM.2001.979398\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 130 nm-generation flash memory technology has been developed, optimized for small cell size, high performance low voltage operation and multi-level-cell and embedded logic capability. Memory cell scaling utilizes the architecture features from the 180 nm technology along with channel erase, advanced 130 nm lithography, dielectric scaling, junction scaling, dual trench and dual spacer technology. 32 Mbit flash memories with a 0.16 um/sup 2/ cell size have been built on this technology showing good yield, performance and reliability.\",\"PeriodicalId\":13825,\"journal\":{\"name\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"volume\":\"14 1\",\"pages\":\"2.5.1-2.5.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2001.979398\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979398","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 130 nm generation high density Etox/sup TM/ flash memory technology
A 130 nm-generation flash memory technology has been developed, optimized for small cell size, high performance low voltage operation and multi-level-cell and embedded logic capability. Memory cell scaling utilizes the architecture features from the 180 nm technology along with channel erase, advanced 130 nm lithography, dielectric scaling, junction scaling, dual trench and dual spacer technology. 32 Mbit flash memories with a 0.16 um/sup 2/ cell size have been built on this technology showing good yield, performance and reliability.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
