2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献_第5页

A 4-54GHz Static Frequency Divider with Back-Gate Coupling 带后门耦合的4-54GHz静态分频器

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373247

Jung-Yu Chang, Shen-Iuan Liu

引用次数: 10

Toward Automatic Synthesis of SOC Test Platforms SOC测试平台的自动合成

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373234

Wen-Cheng Huang, C. Chang, Kuen-Jong Lee

{"title":"Toward Automatic Synthesis of SOC Test Platforms","authors":"Wen-Cheng Huang, C. Chang, Kuen-Jong Lee","doi":"10.1109/VDAT.2007.373234","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373234","url":null,"abstract":"Employing a test platform in an SOC design to execute test procedures can greatly simplify many SOC test problems. It, however, would require tremendous human efforts if the test platform would be generated manually. In this paper, we describe a design automation system, called DASTEP (design automation system for SOC test platform), that is aimed to help users build a test platform and incorporate their IP designs into the platform. DASTEP provides an interactive mode to allow users to modify individual IP cores into 1149.1-or 1500-compatible ones and integrate them into the test platform. For a hierarchical core, DASTEP can synthesize a hierarchical test control architecture such that each core in the hierarchy can be efficiently tested in a 1149.1-compatible manner. All of the test procedures using this test platform are carried out on the chip through the cooperation of an embedded processor that usually exists in an SOC design and a dedicated test-access-mechanism (TAM) controller that can be automatically generated. Appropriate simulation environment that allows the simulation of the entire test flow is also created in conjunction with the generation of the test hardware/software, hence the verification of both core design and test plan can be readily carried out. A friendly graphic user interface tool is also developed that can greatly simplify the generation and simulation of the test platform.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127201533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A Memory-Efficient Progressive JPEG Decoder 一个内存高效的渐进式JPEG解码器

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373198

Kun-Bin Lee, Chi-Cheng Ju

引用次数: 3

Low Power and Power Aware Design for DVB-T/H Baseband Inner Receiver DVB-T/H基带内接收机的低功耗和功耗感知设计

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373245

C. Tseng, Ting-Chen Wei, Wei-Chang Liu, S. Jou

引用次数: 2

An LLC-OCV Methodology for Statistic Timing Analysis 一种用于统计时序分析的LLC-OCV方法

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373199

J. Hong, K. Huang, P. Pong, J. Pan, J. Kang, K.C. Wu

引用次数: 4

Theoretical Analysis and Implementation of a Variable Gain Even Harmonic Mixer 变增益均匀谐波混频器的理论分析与实现

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.372760

J. Hsieh, Shuenn-Yuh Lee

引用次数: 5

On-Chip VDC Circuit for SRAM Power Management 用于SRAM电源管理的片上直流电路

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.372757

C.F. Lee, W. Lin, F. Lai, S.C. Lin

引用次数: 3

Power Gating Technique for Embedded Pseudo SRAM 嵌入式伪SRAM的功率门控技术

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373251

Ching-Yun Cheng, Ming-Hung Chang, W. Hwang

引用次数: 4

A Low-Power Low-Swing Single-Ended Multi-Port SRAM 一种低功耗低摆幅单端多端口SRAM

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373203

Hao-I Yang, Ming-Hung Chang, Ssu-Yun Lai, Hsiang-Fei Wang, W. Hwang

引用次数: 17

A Self-Calibrated Multiphase DLL-Based Clock Generator 基于自校准多相dll的时钟发生器

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373237

Hsin-Shu Chen, Chao-Ching Hung

引用次数: 3