发布求助
文献互助 智能选刊 最新文献

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献

筛选
英文 中文
Multilevel LINC System Design for Wireless Transmitters 无线发射机多电平LINC系统设计
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373246
Yuansi Chen, Kai-Yuan Jheng, A. Wu, H. Tsao, B. Tzeng
{"title":"Multilevel LINC System Design for Wireless Transmitters","authors":"Yuansi Chen, Kai-Yuan Jheng, A. Wu, H. Tsao, B. Tzeng","doi":"10.1109/VDAT.2007.373246","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373246","url":null,"abstract":"Linear amplifier with nonlinear components (LINC) is a power linearization method which offers both high linearity and high power amplifier (PA) efficiency in wireless transmitters. While LINC increases the power efficiency of PAs, this linearization technique requires an extra power combiner which results in low power efficiency of whole system. To improve this drawback, we propose a multi-level LINC (ML-LINC) method to not only increase power combiner efficiency but also maintain high linearity of wireless transmitters. We also derive the optimal value of each scaling level to maximize the power combiner efficiency. Finally, we demonstrate a four-level scaling ML-LINC as a design example which enhances power combiner efficiency from 44.5% to 80.8% and maintains high linearity to fulfill WCDMA specifications.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A Low-Power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length 基于稀疏状态转换和可变截断长度的低功耗维特比解码器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373220
D. Lin, Chien-Ching Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
{"title":"A Low-Power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length","authors":"D. Lin, Chien-Ching Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/VDAT.2007.373220","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373220","url":null,"abstract":"The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114591373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Two-Stage Scattered Pilot Synchronization with Channel Estimation Scattered Pilots Pre-Filling for DVB-T/H 基于信道估计的DVB-T/H两级散射导频同步
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373244
Wei-Chang Liu, Ting-Chen Wei, S. Jou
{"title":"Two-Stage Scattered Pilot Synchronization with Channel Estimation Scattered Pilots Pre-Filling for DVB-T/H","authors":"Wei-Chang Liu, Ting-Chen Wei, S. Jou","doi":"10.1109/VDAT.2007.373244","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373244","url":null,"abstract":"In this paper a two-stage fast scattered pilot synchronization (SPS) scheme is proposed to increase the reliability of scattered pilot synchronization in DVB-T/H. A channel estimation scattered pilots pre-fllling scheme is added to the two-stage fast scattered pilot synchronization scheme and reduces at least one symbol time to the demapping process. By using multi-stage PB-PB (Power-Based) fast scattered pilot synchronization scheme, the performance and reliability is improved with less hardware cost than single stage CB (correlation-based) fast scattered pilot synchronization scheme.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128587775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Characterization of Supply and Substrate Noises in CMOS Digital Circuits CMOS数字电路中电源和衬底噪声的表征
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373256
Hsien-Hung Wu, C. Fu, Yaw-Feng Wang, Pei-Wen Luo, Yen-Ming Chen, L. Cheng, C. Chien
{"title":"Characterization of Supply and Substrate Noises in CMOS Digital Circuits","authors":"Hsien-Hung Wu, C. Fu, Yaw-Feng Wang, Pei-Wen Luo, Yen-Ming Chen, L. Cheng, C. Chien","doi":"10.1109/VDAT.2007.373256","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373256","url":null,"abstract":"The biggest contributors to the substrate noise are supply noises, since the power and ground wires are directly connected to the silicon substrate for CMOS digital cells. Clock trees in large digital designs can acquire large power consumption when thousands of flip-flops transitioning through the switching zone. Memories also draw significant instantaneous power when being accessed. In this paper, a measurement of the substrate noise in conjunction with the supply noises analyses were conducted on a real circuit system. The measured substrate noise waveforms were proportional to the power consumptions and substantially correlated with the supply noises for each test condition. As a result, these observations could be useful for modeling substrate noise effects and developing prevention methods.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124559328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reducing Transaction-Level Modeling Effort while Retaining Low Communication Overhead for HW/SW Co-Emulation System 为软硬件协同仿真系统减少事务级建模工作量，同时保持低通信开销
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373208
Young-Il Kim, Moo-Kyoung Chung, Ando Ki, C. Kyung
{"title":"Reducing Transaction-Level Modeling Effort while Retaining Low Communication Overhead for HW/SW Co-Emulation System","authors":"Young-Il Kim, Moo-Kyoung Chung, Ando Ki, C. Kyung","doi":"10.1109/VDAT.2007.373208","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373208","url":null,"abstract":"This paper presents a new scheme that reduces the modeling efforts of a transactor while retaining the performance of transaction-based verification for hardware/software co-emulation system. The conventional transaction-based verification requires the designer to develop a synthesizable transactor which interfaces with unfamiliar emulation-system-dependent protocol. The proposed method locates the transactor in the software side instead of in the hardware emulator. This allows easy-to-develop transactor described in high-level language. To reduce the communication time between testbench and DUT, we make the signal flow uni-directional by exploiting existing HDL testbench. The experimental results show that the proposed method is applicable to real-world test environment.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115929942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector 快速锁定双电荷泵模拟DLL使用改进的相位频率检测器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.372761
Soh Lip-Kai, M. Sulaiman, Z. Yusoff
{"title":"Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector","authors":"Soh Lip-Kai, M. Sulaiman, Z. Yusoff","doi":"10.1109/VDAT.2007.372761","DOIUrl":"https://doi.org/10.1109/VDAT.2007.372761","url":null,"abstract":"In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog DLL takes up less area compared to other similar fast lock analog DLL due to the reduction of the number of phase frequency detector (PFD) used in the design. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and output signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-mum 1P6M CMOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 mum x 116.16 mum. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking and low jitter properties.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131992636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Mixed Hardware Software Multilevel Modeling and Simulation for Multithreaded Heterogeneous MPSoC 多线程异构MPSoC的混合软硬件多级建模与仿真
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373215
K. Popovici, X. Guerin, L. Brisolara, A. Jerraya
{"title":"Mixed Hardware Software Multilevel Modeling and Simulation for Multithreaded Heterogeneous MPSoC","authors":"K. Popovici, X. Guerin, L. Brisolara, A. Jerraya","doi":"10.1109/VDAT.2007.373215","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373215","url":null,"abstract":"In this paper, we introduce a mixed hardware -software architecture model to abstract hardware-software interfaces of multithreaded heterogeneous multiprocessor architecture with specific hardware I/O. We use Simulink environment as modeling language to capture this representation. We generate two intermediate simulation models called Virtual Architecture and Transaction Accurate to validate the software during the different design steps. The software refinement is performed by automatic software code generation for parallel application from Simulink model, and automatic low level software customization for specific architecture. Through experiments we show the efficiency of the proposed design flow that decreases design time without affecting design quality.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127631640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
4-Mb SPI Flash Compatible Phase-Change Memory 4mb SPI闪存兼容相变存储器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373202
S. Sheu, Lieh‐Chiu Lin, Wen-Han Wang, P. Chiang, K. Su, M. Kao, M. Tsai
{"title":"4-Mb SPI Flash Compatible Phase-Change Memory","authors":"S. Sheu, Lieh‐Chiu Lin, Wen-Han Wang, P. Chiang, K. Su, M. Kao, M. Tsai","doi":"10.1109/VDAT.2007.373202","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373202","url":null,"abstract":"A 4-Mb with SPI serial interface phase-change memory which is completely compatible with the traditional SPI flash memory is implemented in this study. The peripheral circuit is much simpler than flash memory. The 512 Kb sector erase time is less than 7 ms while the 4 Mb bulk erase time is 80 ms only.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133795256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
JQRPSD Detection with Low Complexity for SDM MIMO Wireless Communication System 低复杂度的SDM MIMO无线通信系统JQRPSD检测
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373228
Hsin-Lei Lin, H. Chen, R. Chang
{"title":"JQRPSD Detection with Low Complexity for SDM MIMO Wireless Communication System","authors":"Hsin-Lei Lin, H. Chen, R. Chang","doi":"10.1109/VDAT.2007.373228","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373228","url":null,"abstract":"A detection of joint QR decomposition and partial sphere decoder (JQRPSD) method with low complexity is proposed in this paper. The purpose of the detection is reducing complexity from sphere decoder and having better performance than successive cancellation detection with QR decomposition (QR-SCD) and vertical Bell laboratories layered space-time (V-BLAST). In a perfect channel estimated receiver, the simulation of JQRPSD method performs the performance approaching the performance of sphere decoder algorithm. The proposed detector is designed by TSMC 0.18 mum CMOS technology without preprocessor in 4 x 4 multiple input and multiple output (MIMO) wireless communication.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116347368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low Cost Testing of Quadruple Band GSM RFCMOS SOC 四频段GSM RFCMOS SOC的低成本测试
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373217
B. Lai, C. Rivera, K. Waheed
{"title":"Low Cost Testing of Quadruple Band GSM RFCMOS SOC","authors":"B. Lai, C. Rivera, K. Waheed","doi":"10.1109/VDAT.2007.373217","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373217","url":null,"abstract":"Modern RF integrated SOC (system on a chip) are becoming increasingly more complex as more and more functions are being integrated on-chip. This is driving the test cost to be higher due to increased design complexity, resulting in greater tester complexity and longer tests times. In this paper, we will describe how we have implemented a low cost multi-site RF test solution for the industry's first single-chip 90 nm RFCMOS GSM transceiver with integrated cellular base-band modem [1,2]. We will illustrate novel methods of performing a Gaussian minimum shift keying (GMSK) spectrum mask test and phase trajectory error (PTE) test as defined in the GSM transmitter specifications. We also demonstrate receiver signal measurements such as gain, received IQ amplitude and phase imbalance, and noise figure (NF) for a GSM receiver. The driving motivation for this work is to enable the use of low cost multi-site testers for RF applications with high test stability and throughput in a production environment.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129151948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信