S. Sheu, Lieh‐Chiu Lin, Wen-Han Wang, P. Chiang, K. Su, M. Kao, M. Tsai
{"title":"4mb SPI闪存兼容相变存储器","authors":"S. Sheu, Lieh‐Chiu Lin, Wen-Han Wang, P. Chiang, K. Su, M. Kao, M. Tsai","doi":"10.1109/VDAT.2007.373202","DOIUrl":null,"url":null,"abstract":"A 4-Mb with SPI serial interface phase-change memory which is completely compatible with the traditional SPI flash memory is implemented in this study. The peripheral circuit is much simpler than flash memory. The 512 Kb sector erase time is less than 7 ms while the 4 Mb bulk erase time is 80 ms only.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"4-Mb SPI Flash Compatible Phase-Change Memory\",\"authors\":\"S. Sheu, Lieh‐Chiu Lin, Wen-Han Wang, P. Chiang, K. Su, M. Kao, M. Tsai\",\"doi\":\"10.1109/VDAT.2007.373202\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 4-Mb with SPI serial interface phase-change memory which is completely compatible with the traditional SPI flash memory is implemented in this study. The peripheral circuit is much simpler than flash memory. The 512 Kb sector erase time is less than 7 ms while the 4 Mb bulk erase time is 80 ms only.\",\"PeriodicalId\":137915,\"journal\":{\"name\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2007.373202\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2007.373202","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4-Mb with SPI serial interface phase-change memory which is completely compatible with the traditional SPI flash memory is implemented in this study. The peripheral circuit is much simpler than flash memory. The 512 Kb sector erase time is less than 7 ms while the 4 Mb bulk erase time is 80 ms only.